Abstract: Register pull-out for sequential circuit blocks may include determining, using computer hardware, a net of a circuit design having a driver that is a macro circuit block driving a plurality of loads and determining, using the computer hardware, a placement difficulty of the net based upon a type of the driver and number and type of the plurality of loads. In response to determining that the placement difficulty of the net exceeds a threshold placement difficulty, the computer hardware is capable of modifying the circuit design by pulling a register from the driver to a location on a device external to the driver and changing internal logic of the driver based upon the pulled register.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.

Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design awareness. Embodiments may include providing, using a processor, an electronic design having a package layout and a die layout associated therewith. Embodiments may also include displaying at a graphical user interface, the package layout and allowing, at the graphical user interface, a user to edit the package layout. Embodiments may further include determining, using the processor, an impact of the edit on the die layout and in response to the edit, mirroring the edit at the die layout.

Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

Abstract: In an electronic circuit design system, dynamic visual guidance for relative placement of mutually paired electronic components, such as a bypass capacitance portion and a power pin in a power domain, is provided. A first, selected component is adaptively paired with one of a plurality of second components eligible for pairing with the first component, according to predetermined pairing criteria such as proximity criteria. A mutual placement zone between the paired components is generated to define a locus of valid placement locations of the paired first and second components one with respect to the other according to predetermined placement criteria therefor. Visual indicia to represent the mutual placement zone is generated, thereby providing visual guidance to reposition the first component.

Abstract: In some embodiments, a method for processing register transfer level code representing a circuit design can include: determining, by one or more processors based on the register transfer level code, a first group of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each of the group of signal transitions represents a nondeterministic transition from a first signal state to one or more other signal states; determining, at least one of the processors based on the register transfer level code, that a subgroup of signal transitions of the first group is glitch-free; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the glitch-free subgroup.

Abstract: A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

Abstract: Embodiments describing an approach to detecting negative paths for a circuit design based on a circuit timing test of the circuit design. Assigning each negative path to a logic bucket, an integration bucket, or a macro bucket, wherein the logic bucket corresponds to logic design flaws, the integration bucket corresponds to integration design flaws, and the macro bucket corresponds to macro design flaws or design flaws residing within a macro of the circuit design. Detecting a modification to the circuit design based on the logic design flaws, the integration design flaws, and the macro design flaws, and applying the modification to the circuit design to enable manufacturing an integrated circuit, wherein an overall delay between two latches of the integrated circuit is below a predetermined threshold.

Abstract: Disclosed approaches for processing a circuit design include determining first slacks of cells, including a target cell, coupled to receive a clock signal through a first clock leaf. The first slacks are based on a current delay value specified for a first programmable delay circuit. The method predicts second slacks of the cells based on another delay value specified for the first programmable delay circuit, and then determines whether or not the second slacks indicate a degradation in timing relative to the first slacks. The current delay value of the first programmable delay circuit is adjusted to the other delay value in response to determining the second slacks indicates no degradation in timing. The target cell is reconnected to receive the clock signal from a second clock leaf having a second programmable delay circuit specified with the other delay value in response to determining the second slacks indicates degradation in timing.

Abstract: A design support apparatus includes a storage that stores first layout data and pattern data, the first layout data indicating a circuit pattern of a design target circuit, the circuit pattern including circuit patterns, dummy patterns of the component circuits, and a wiring pattern, the component circuits being included in the design target circuit, the pattern data indicating a second dummy pattern, the second dummy pattern having a shape different from a shape of a first dummy pattern, the first dummy pattern being included in the first layout data, and a processor coupled to the storage, configured to specifies a component circuit, the specified component circuit being included in an area in the arrangement area, extracts pattern data indicating a dummy pattern, generates second layout data, the second layout data indicating a circuit pattern, and outputs the second layout data.

Abstract: A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.

Abstract: In some embodiments, a method for processing register transfer level code representing a circuit design. The method can include determining, by one or more processors based on the register transfer level code, an input sequence of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each signal transition represents a nondeterministic transition from a first signal state to one or more possible signal states; determining, at least one of the processors based on the register transfer level code, that a subsequence of signal transitions of the input sequence indicates at most one transition within the subsequence; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the input sequence of signal transition.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further include performing model checking based upon, at least in part, the property and the one or more elements. Embodiments may also include verifying the property and generating an unsatisfiability core based upon, at least in part, the one or more elements.

Abstract: A circuit arrangement, in particular for a safety I&C system of a nuclear power plant, keeps a proven diagram-centric project-specific engineering approach known from CPU-based systems while reaping the benefits of FPGA technology. To this end, the circuit arrangement includes: a generic FPGA with a plurality of logic blocks, and at least one dedicated PLD which operates as an application-specific switch-matrix for the logic blocks.

Abstract: A semiconductor device is provided. A semiconductor device includes a filler cell including first and second insulating structures, the first and second insulating structures extending in a first direction, the filler cell being defined by first cell boundaries; and a neighboring cell including a third insulating structure, the third insulating structure extending in the first direction, the neighboring cell being adjacent to the filler cell in the first direction and defined by second cell boundaries, wherein the first and second insulating structures are spaced apart from one another in a second direction, is the second direction being perpendicular to the first direction.

Abstract: A method of geometry corrections to properly transfer semiconductor designs on a wafer or a mask in nanometer scale processes is provided. In contrast with some prior art techniques, geometry corrections and possibly dose corrections are applied before fracturing. Unlike edge based corrections, where the edges are displaced in parallel, the displacements applied to generated geometry corrections do not preserve parallelism of the edges, which is specifically well suited for free form designs. A seed design is generated from the target design. Vertices connecting segments are placed along the seed design contour. Correction sites are placed on the segments. Displacement vectors are applied to the vertices. A simulated contour is generated and compared to the contour of the target design. The process is iterated until a match criteria between simulated and target design (or another stop criteria) is reached.

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

Abstract: A carrier, such as a battery, that queries a memory of a charger or charging circuit, or the memory of equipment or discharging circuit powered by the battery, to determine the relative date or version of data, operating parameters and/or software on both the battery and the equipment, and either provides updated data, operating parameters and/or software to the equipment, or retrieves later dated data, operating parameters and/or software from the equipment to update the memory of the battery and/or further distribute the updated data, operating parameters and/or software to other batteries or equipment.