Abstract: A method of managing an energy storage system that includes a plurality of smart energy storage cells, and a related method of operation for said smart cells. The cells are arranged into a two-dimensional array, and at least one management unit for controlling and monitoring the smart cells is coupled to the array. The smart cells and management units engage in wireless communication that has relatively short range and is relatively directional, with the direction being electronically-steerable in the plane of the array. The management method assigns direction codes to each smart cell which the cells utilize to steer the directions of their communication links, thereby organizing the smart cells into a plurality of serially-linked communication networks. The methods include steps for automatically determining the size and arrangement of the array, including the orientation of each smart cell.

Abstract: A method includes, for a first tool-log variable of a set of tool-log variables, comparing a first tool-log variable result from a first integrated circuit (IC) manufacturing recipe to a first tool-log variable result from a second IC manufacturing recipe. The set of tool-log variables corresponds to one or more tool-logs generated from execution of the first IC manufacturing recipe and the second IC manufacturing recipe on an IC manufacturing tool. Based on the comparison, a first tool-log variable similarity value for the first tool-log variable is assigned, and, based on the first tool-log variable similarity value, a recipe similarity value for the first IC manufacturing recipe and the second IC manufacturing recipe is calculated. At least one of comparing the first tool-log variable results, assigning the first tool-log variable similarity value, or calculating the recipe similarity value is performed by a processing device.

Abstract: A system and method to automatically determine power plane shape in a printed circuit board (PCB) involve obtaining inputs. The inputs include a size and shape of the PCB, a set of sources, and a set of sinks associated with a power plane. The method also includes determining a center of charge (CoC) as a center of largest current density for the set of sources and the set of sinks, and creating a sub-shape corresponding with a path from each source of the set of sources and from each sink of the set of sinks to the CoC. The creating the sub-shape includes determining a width of a conductor in the path corresponding with each of the sub-shapes. The sub-shapes created for the set of sources and the set of sinks are combined as the power plane shape.

Abstract: A battery system includes a position detector configured to detect whether a first battery protector is coupled to a second power rail and positioned at a bottom of a stack. A cell balancing input (CBI) is coupled to receive a CBI signal to enable or disable cell balancing of the first battery protector. A cell balancing output (CBO) enables cell balancing of a second protector in the stack.

Abstract: An equivalent circuit is capable of, while having a simple configuration, accurately expressing a superposition characteristic and having excellent practicality and workability. A current sensor and a voltage source are connected in series between external terminals of an equivalent circuit. A reference state element having an impedance forms a closed loop with a current source. A current flowing through the equivalent circuit and detected by the current sensor is reproduced by the current source and then applied to the reference state element, so that a potential difference is generated across the reference state element. A voltage obtained by multiplying the potential difference by a correction coefficient is outputted by the voltage source. By setting the correction coefficient to be dependent on the current or an inter-terminal voltage, the impedance represented by the equivalent circuit can be reproduced as a characteristic dependent on the current I or the inter-terminal voltage.

Abstract: Methods and computer-readable media for testing integrated circuit designs implement a physically efficient scan by optimally balancing and connecting scan segments in a 2-dimensional compression chain architecture. A compression architecture that provides an optimal and balanced configuration of scan segments in 2D compression grids to not only decrease test time, but also to maximize compression efficiency and limit wiring congestion for IC designs that contain complex scan segments facilitates efficient scanning of data by bisecting the elements into balanced partitions of the same target scan length. A segment padding algorithm, followed by a bisecting algorithm and ultimately an element swapping algorithm may be applied to optimally balance and connect scan segments in 2-D compression chains, optimizing an efficient compression architecture which minimizes scan testing resources and time.

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

Abstract: A new low-power test compression method and design for testability (DFT) architecture are proposed for deterministic test pairs for launch-on-capture (LOC) transition fault testing by using a new seed encoding scheme, a new low-power test application procedure and a new test compression architecture. The new seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set. The low-power test compression architecture includes: (1) the LFSR established by the selected primitive polynomial and the selected number of extra variables injected to the LFSR; (2) the scan tree architecture for LOC transition fault testing; and (3) the new gating technique. A new static test compaction scheme is proposed by bitwise modifying the values of a seed and the extra variables. A new technique for test point insertion is proposed for LOC delay testing in the two-frame-circuit model, which apparently reduces test data volume.

Abstract: A child component ID module identifies child components connected to a parent component in response to selection of the parent component for placement on a PCB. The child components identified from component connections of a logic design. A child placement module places the child components around the parent component after placement of the parent component, where each child component is placed in compliance with constraints of the child components. A constraint highlight module identifies, on a PCB layout, an allowable area for component placement and prohibited areas for non-placement after selection of the component. The component is a parent component or a child component identified from component connections of a logic design of an electronic circuit design. The apparatus includes a constraint de-highlight module that removes identification on the PCB layout of the allowable area and the one or more prohibited areas in response to placement of the component.

Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from a sampling circuit of one or more receiver arrangements that are not in autozero mode. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

Abstract: The present invention is a process by which an engineer can provide as input the design, functional verification goals, and other abstract design details, and receive as output an agent which can be integrated into traditional test benches and will generate stimuli to automatically hit the functional coverage goals for the design. The present invention may employ a system which includes a learning configurator, a learning-based test generator, and a test bench. The learning test generator is communicatively coupled to the generator and notably comprises a learning algorithm.

Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.

Abstract: A system for controlling a state of charge (SOC) of a battery includes a battery SOC control apparatus for controlling a revolution per minute (RPM) of an air blower based on the SOC of the battery and a number of charge/discharge cycles of the battery in a case where a vehicle is in a constant current driving state, and a memory device for storing the SOC of the battery calculated by the battery SOC control apparatus.

Abstract: A computer-implemented method designs a distributed heterogeneous computing and control system, including both an application and a hardware context and configuring the application in the hardware context. The method is implemented by design software instructions executing in a computer node, associated with an interactive display, to establish an interactive environment utilizing computer processes. The computer processes provide access in the interactive environment to a set of functional modules and a set of primitive modules. The computer processes receive the interactive environment a selection of desired ones of the functional modules and the primitive modules and order them in a manner to characterize the distributed computing and control system as a schematic of a set of devices. The computer processes parse the schematic to produce a set of sub-schematics that each correspond to a distinct device in a set of devices in the distributed computing and control system.

Abstract: The disclosed herein relates to method for persistence during placement optimization of an integrated circuit design. The method comprises performing cluster operation by grouping of a plurality of cells into a plurality of mobs. The method further comprises performing a spreading operation by moving the plurality of mobs and the plurality of cells simultaneously to optimize empty space of the integrated circuit design.

Abstract: Pre-silicon fairness evaluation to detect fairness issues pre-silicon. Drivers drive a plurality of commands on one or more interfaces of a device under test to test the device under test. State associated with the device under test is checked. Based on the state, a determination is made as to whether the drivers are to continue driving commands against the device under test. Based on determining that the drivers are to continue driving the commands, a further determination is made as to whether a predefined limit has been reached. Based on determining the predefined limit has been reached, ending the test of the device under test in which the test fails.

Abstract: Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.

Abstract: Pre-silicon fairness evaluation to detect fairness issues pre-silicon. Drivers drive a plurality of commands on one or more interfaces of a device under test to test the device under test. State associated with the device under test is checked. Based on the state, a determination is made as to whether the drivers are to continue driving commands against the device under test. Based on determining that the drivers are to continue driving the commands, a further determination is made as to whether a predefined limit has been reached. Based on determining the predefined limit has been reached, ending the test of the device under test in which the test fails.

Abstract: Method and apparatus for analyzing an electrical circuit design includes storing within a memory associated with a pin, a pin functional definition comprising a pin connection parameter, and comparing the pin connection parameter to a design parameter to determine a result pertaining to a pin connection. The memory may be internal or external to the pin.

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.