Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

Abstract: A method is utilized to calculate a boundary leakage in a semiconductor device. A boundary is detected between a first cell and a second cell, which the first cell and the second cell are abutted to each other around the boundary. Attributes associated with cell edges of the first cell and the second cell are identified. A cell abutment case is identified based on the attributes associated with the cell edges of the first cell and the second cell. An expected boundary leakage between the first cell and the second cell is calculated based on leakage current values associated with the cell abutment case and leakage probabilities associated with the cell abutment case.

Abstract: Methods and apparatus for pattern matching and classification are disclosed. In one example of the disclosed technology, a method of performing pattern matching according to a puzzle-matching the methodology includes analyzing an original source layout pattern and determining a signature for the original source layout pattern. A target layout is scanned to search for one or more portions of the target layout that have a signature that matches or is similar to the signature of the original source pattern. Similar patterns are searched based on a signature comparison of the source pattern and the target layout. In some examples of the disclosed technology, it is possible to match partial context to the original source pattern. In some examples, matches can be made in the target layout for different orientations of layout.

Abstract: A timing fixing logic section may select a timing path from among a plurality of timing paths. For the selected timing path, multiple nets along the path may be traversed. For a particular net, multiple metal layers may be traversed. For a particular metal layer, multiple shapes that are associated with the particular net may be traversed. A timing fixing logic section may examine space that is nearby each of the shapes, and identify unused space. The timing fixing logic section may add an extension metal section to the shape. In addition, the timing fixing logic section may identify an existing via of a first type, and select an alternate via of a second type having a resistance that is higher or lower than the existing via. The existing via may be replaced with the alternate via. Accordingly, hold and setup timing of a circuit may be improved.

Abstract: A computer-implemented method characterizes and controls performance of a set of device nodes in a distributed heterogeneous computing and control system. The device nodes are in physically distinct locations, in communication with one another over a network. One or more of the device nodes require different application programming code due to differences in hardware configuration or software configuration. The method includes configuring, by a design computer, for introduction into each distinct one of the device nodes, a corresponding communication facility and a corresponding dashboard instance. After introduction of the communication facility and dashboard instance into each device node, the design computer includes a communication facility in communication with the corresponding communication facility of each device node.

Abstract: A charging path switching circuit includes a first port, a second port, a path switch unit, and a conversion unit. The first port is connected to an external electronic device to obtain a first electrical signal. The second port is connected to an external power source to obtain a second electrical signal. The conversion unit is connected the path switch unit and converts the first electrical signal or the second electrical signal to a predetermined voltage. The path switch unit is connected to the first port and the second port. The path switch unit selects to connect to the first port or the second port, to obtain the first electrical signal or the second electrical signal according to the connection of the first and the second port. The path switch unit preferentially selects to obtain the second electrical signal from the second port.

Abstract: Integrated circuits may implement a filter to identify items in a data store that match a regular expression by sharing character data across lookups in the filter. The NFA states of the may be programmed responsive to a query that includes a regular expression. The NFA states may include a character decode stage that operates on one portion of character bits, while another portion of character bits is evaluated at a state detection stage that also evaluates an output value of the character decode stage.

Abstract: Devices, methods, computer readable media, and other embodiments are described for automated formal analysis and verification of a circuit design. One embodiment involves accessing a circuit design and a set of default verification targets for the circuit design. A plurality of partitions for the circuit design are then automatically generated, and a first partition is analyzed to generate a first set of verification targets for the first partition based on the set of default verification targets and a set of partition and schedule values for the first partition. A first formal verification analysis is performed on the first partition, the first set of verification targets, and the set of partition and schedule values, and a formal verification output is generated based on the first formal verification analysis. Various embodiments can additionally involve stagnation analysis and additional automation to customize the analysis for each partition.

Abstract: Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.

Abstract: A method of probing a multidimensional parameter space of battery cell test protocols is provided that includes defining a parameter space for a plurality of battery cells under test, discretizing the parameter space, collecting a preliminary set of cells being cycled to failure for sampling policies from across the parameter space and include multiple repetitions of the policy, specifying resource hyperparameters, parameter space hyperparameters, and algorithm hyperparameters, selecting a random subset of charging policies, testing the random subset of charging policies until a number of cycles required for early prediction of battery lifetime is achieved, inputting cycle data for early prediction into an early prediction algorithm to obtain early predictions, inputting the early predictions into an optimal experimental design (OED) algorithm to obtain recommendations for running at least one next test, running the recommended tests by repeating from the random subset testing step above, and validating final

Abstract: Methods, systems and devices for using charged particle beams (CPBs) to write different die-specific, non-volatile, electronically readable data to different dies on a substrate. CPBs can fully write die-specific data within the chip interconnect structure during the device fabrication process, at high resolution and within a small area, allowing one or multiple usefully-sized values to be securely written to service device functions. CPBs can write die-specific data in areas readable or unreadable through a (or any) communications bus. Die-specific data can be used for, e.g.: encryption keys; communications addresses; manufacturing information (including die identification numbers); random number generator improvements; or single, nested, or compartmentalized security codes. Die-specific data and locations for writing die-specific data can be kept in encrypted form when not being written to the substrate to conditionally or permanently prevent any knowledge of said data and locations.

Abstract: Disclosed is a method of hardware and firmware debugging. The method includes coupling an interface sniffer to an interface of the hardware component on which firmware is running such that the interface sniffer captures a transaction on the interface that is associated with the hardware component, coupling, to the interface sniffer, a simulator including a reference model to receive the captured transaction by the simulator such that the captured transaction affects the reference model, and causing the internal state of the hardware component to be reproduced in the simulator based on the reference model affected by the captured transaction.

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

Abstract: In an embodiment, a method for designing an integrated circuit with target characteristics uses a physical design graph. The physical design graph includes a plurality of physical design sub-configurations, each of the plurality of physical design sub-configurations including a placement of a group of physical cells and having annotated characteristics. The method includes partitioning an integrated circuit electrical design into a plurality of electrical design sub-configurations, including a specific electrical design sub-configuration requiring a specific group of the physical cells. The method includes selecting from the physical design graph, based on the required specific group of the physical cells and the target characteristics, a physical design sub-configuration including the specific group of the physical cells in a specific placement and having the target characteristics. The method includes determining an integrated circuit physical design for manufacturing the integrated circuit.

Abstract: Integrated circuit failures caused by metastability related to assertion of asynchronous resets frequently escape detection before fabrication, causing design respins and severe economic loss. The numerous reset signals, flip-flops and complex logical interactions inherent in an integrated circuit cause an analysis for reset-metastability failures to be extremely noisy, reporting an unmanageable number of false failures and making early removal of failures impractical. Said noisy reporting arises because many flip-flops where reset-metastability manifests do not necessarily cause overall failure. An effective analysis of reset-metastability failures must identify all potential failures, but also must only report true failure potential. The present invention maximizes noise reduction by applying special conditions to identify flip-flops manifesting reset-metastability without causing integrated circuit failure, which can thereby be deemed safe.

Abstract: The invention relates to a system for battery cell balancing comprising a cell monitoring block (16) configured to monitor the voltage or a related quantity across individual cells (C.sub.1, C.sub.2, . . . C.sub.N) in a battery cell module; a microcontroller (18) configured for monitoring the positive terminal voltage (12) and the negative terminal voltage (13) of said battery cell module, and for monitoring (11) the output current I.sub.mod of said module, and monitored cell voltage of said individual cells (C.sub.1, C.sub.2, . . . C.sub.N), where the microcontroller (18) is configured to provide a control signal (20) based at least said positive terminal voltage (12), said negative terminal voltage (13), said output current I.sub.mod of said module, and said monitored cell voltage of said individual cells; and a hybrid module balancing block configured to provide either an active or a passive cell balancing or a combination of active and passive cell balancing of the cells (C.sub.1, C.sub.2, . . . C.sub.

Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.

Abstract: A multi-functional wearable with modular attachments is provided. A case with a first and second connector are provided that can each connect to one or more removable modules, such as a charging cable, lanyard, body strap, name badge, key ring, power brick, and/or battery module. The battery module includes a control panel with a power button to control power from the battery and one or more status LEDs to indicate the charge status of the battery. The battery module also provides storage to hold a cable and/or device. Alternatively, magnets and a first female receptacle that compliments and receives a male connector from a lanyard and a second female connector to connect to another cable may be utilized. The charging cable may be surrounded by fabric or similar material and the charging cable ends may also include one or more magnets or mechanical protrusions.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing electronic designs with electronic design simplification techniques. These techniques identify an input for simplifying an electronic design and generates a simplified electronic design at least by performing layout simplification on the electronic design. A characterization input may be determined for subsequent characterization of the simplified electronic design. An electromagnetic behavior of the simplified electronic design may then be characterized using at least the characterization input.

Abstract: In an example, a configurable block for a programmable device of a plurality of programmable devices in an integrated circuit (IC) includes a first flip-flop having a data port coupled to an output of an interface block of the programmable device, a clock port coupled to a first clock input, and an output port coupled to a first output. The configurable block further includes a second flip-flop having a data port coupled to the output of the interface block, a clock port coupled to the first clock input, and an output port coupled to a second output, and a first multiplexer having a first input port coupled to the output port of the first flip-flop, and a second input port coupled to the output port of the second flip-flop. The configurable block further includes a third flip-flop having an input port coupled to an output of the first multiplexer, a clock port coupled to a second clock input, and an output port coupled to a third output.