Abstract: An intelligent rechargeable battery pack having a battery management system for monitoring and controlling the charging and discharging of the battery pack is described. The battery management system includes a memory for storing data related to the operation of the battery, and the battery management system is also configured to communicate the data related to the operation of the battery to other processors for analysis.

Abstract: A method including: determining a value of a characteristic of a patterning process or a product thereof, at a current value of a processing parameter; determining whether a termination criterion is met by the value of the characteristic; if the termination criterion is not met, determining a new value of the processing parameter from the current value of the processing parameter and a prior value of the processing parameter, and setting the current value to the new value and repeating the determining steps; and if the termination criterion is met, providing the current value of the processing parameter as an approximation of a value of the processing parameter at which the characteristic has a target value.

Abstract: A wireless power system may include an accessory configured to transfer or relay wireless power to a portable electronic device. The portable electronic device may include wireless charging circuitry and sensors configured to detect compatible accessories currently coupled with the portable electronic device. The portable electronic device performs wireless charging or related functions in accordance with the coupled accessories.

Abstract: A charging system for transmitting an electric charging current to an energy receiver including: a charging plug for coupling to a corresponding connecting apparatus; an electronic control device; and at least one temperature sensor for determining a temperature of a current-carrying component of the charging system. The temperature sensor is coupled to the electronic control device for outputting temperature measurement data which represents the temperature of the current-carrying component. The charging system further has an ambient temperature sensor for determining an ambient temperature of the charging system and is coupled to the electronic control device.

Abstract: A portable power source for power tools. The portable power source includes a housing defining a battery support and an power outlet, a circuit supported by the housing and including an input terminal on the battery support, an output terminal on the power outlet, and an inverter electrically connected between the input terminal and the output terminal, a battery power source including a battery housing supported on the battery support, at least one battery cell, and a battery terminal connected to the battery cell and electrically connectable to the input terminal, power being transferrable from the battery cell to the circuit to be output through the power outlet, and a frame connected to the housing and extending beyond a periphery of the housing and of the supported battery power source, the frame inhibiting contact with the housing and the battery power source.

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

Abstract: A lithographic process is performed on a set of semiconductor substrates consisting of a plurality of substrates. As part of the process, the set of substrates is partitioned into a number of subsets. The partitioning may be based on a set of characteristics associated with a first layer on the substrates. A fingerprint of a performance parameter is then determined for at least one substrate of the set of substrates. Under some circumstances, the fingerprint is determined for one substrate of each subset of substrates. The fingerprint is associated with at least the first layer. A correction for the performance parameter associated with an application of a subsequent layer is then derived, the derivation being based on the determined fingerprint and the partitioning of the set of substrates.

Abstract: A mobile device includes an outer package, a first solar panel, and a controller. The first solar panel includes a plurality of first photoelectric converters generating electrical power based on light which enters from a first surface of the outer package and being disposed side by side. The controller determines a magnitude of a light volume of light entering the first solar panel for each of the plurality of the first photoelectric converters, and executes notification processing of transmitting an instruction to provide a notification based on a total number of first photoelectric converters whose light volume is determined to be large in the plurality of the first photoelectric converters.

Abstract: Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan.

Abstract: A statistical single-input switching (SIS) timing value is obtained for a first input of a device. A side input with an arc to a common output of a circuit is selected and a statistical skew for the first input and the selected side input of the circuit is obtained. An expected-value for a statistical scale factor distribution is convolved and computed based on the statistical skew. The statistical single-input switching (SIS) timing value is scaled with a final effective statistical scale factor based on the expected-value; optionally, sensitivities of the statistical timing value to variational parameters are chain-ruled with the sensitivities of the statistical skew to variational parameters; and a statistical timing analysis of a given VLSI design is generated based on the scaled (and optionally, chain-ruled) statistical single-input switching (SIS) timing value to create the improved VLSI circuit design.

Abstract: Techniques for verification of integrated circuit design are disclosed. A design relating to an integrated circuit is received (102). The design includes a first parameterized element and a second parameterized element (104). The first parameterized element is identified as a do-not-care (DNC) element based on usage of the first parameterized element in the design (106). A plurality of models relating to the design are generated by a processing device (110). A first value of the first parameterized element is not varied during the generating, based on the identification of the first parameterized element as a DNC element (108). A second value of the second parameterized element is varied during the generating (108).

Abstract: Disclosed is a battery pack temperature detection system, comprising: a battery pack disposed with a plurality of temperature monitoring points; a plurality of sampling circuits, wherein each temperature monitoring point is disposed with at least two of the plurality of sampling circuits, and the at least two of the plurality of sampling circuits disposed for one temperature monitoring point are different sampling circuits; and a control module configured to acquire temperature data of each temperature monitoring point by each of the disposed sampling circuits, and determine a current temperature of the battery pack according to the temperature data to determine whether the temperature of the battery pack exceeds a preset value.

Abstract: A charging apparatus includes a plurality of batteries, a changeover relay that can be changed over between a first state where the plurality of the batteries are connected in series to one another and a second state where the plurality of the batteries are connected in parallel to one another, an electric storage device, a main relay that is provided between the electric storage device and an electric load of a vehicle, and a control device that controls the opening/closing of the changeover relay. The control device renders the changeover relay in the first state when the main relay is in an open state.

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some embodiments to route the networks on the layers within a certain range that has very close resistance/capacitance (RC) characteristics, and can permit routing each network on layers having the smallest RC characteristic difference.

Abstract: A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

Abstract: A method includes obtaining, for each particular feature of a plurality of features of a device pattern of a substrate being created using a patterning process, a modelled or simulated relation of a parameter of the patterning process between a measurement target for the substrate and the particular feature; and based on the relation and measured values of the parameter from the metrology target, generating a distribution of the parameter across at least part of the substrate for each of the features, the distribution for use in design, control or modification of the patterning process.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Abstract: Systems and methods are disclosed for pad ring generation for integrated circuits. For example, a method may include accessing a pad ring configuration data structure, wherein the pad ring configuration data structure declares rules for inputs and outputs of an integrated circuit using a scripting language; based on the pad ring configuration data structure, automatically generating an integrated circuit design data structure that encodes a physical design for the integrated circuit that includes a pad ring with bumps satisfying the rules for inputs and outputs of the integrated circuit and also includes a placeholder for additional logic circuits, wherein the placeholder includes connections to one or more input drivers of the pad ring and to one or more output drivers of the pad ring; and transmitting, storing, or displaying the integrated circuit design data structure.

Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design using track patterns while conforming to the requirements of complex color based track systems, and using information about instances that have been included in the design. According to some aspects, the present embodiments provide “Dynamic Width Space Patterns (DWSP)” which are WSPs that are modified dynamically in consideration of neighboring geometries such that shapes created or edited using WSPs are design rule compliant. Embodiments can include providing visual indicators in a display of a portion of a design that is being created or edited, as well as possibly other alerts, so as assist a designer in creating a design rule compliant integrated circuit design that is also subject to WSPs.

Abstract: A power network includes a plurality of power switch units disposed in a first semiconductor layer, arranged in a plurality of columns along a first direction and a plurality of rows along a second direction. The power switch units in even rows are aligned with a center point of a horizontal space between adjacent two of the power switch units in the same row of the odd rows of the power switch units in the first direction. The power switch units in even columns are aligned with a center point of a vertical space between adjacent two of the power switch units in the same column of the odd columns of the power switch units in the second direction. The power network further includes a plurality of second connecting lines disposed in a fourth semiconductor layer and extending in the second direction.