Patents Examined by Helen Rossoshek
  • Fast charging station with charging cable and temperature control device for the charging cable
    Patent number: 10894479
    Abstract: A charging cable device for a fast charging station for fast charging a battery of a vehicle with an electric drive, having a temperature control device, and a charging cable connected thereto. The charging cable has a multiplicity of fluid lines which extend from an end of the charging cable facing the temperature control device to an end facing away from the temperature control device, and are connected to one another at the end facing away from the temperature control device. The temperature control device is connected to the fluid lines of the charging cable to form a fluid circuit. The temperature control device is designed to heat a fluid in the fluid circuit. Also disclosed is a fast charging station for fast charging a battery of a vehicle with an electric drive. The fast charging station has a charging cable device at the top.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: January 19, 2021
    Assignee: Dr. Ing. h.c. F. Porsche Aktiengesellschaft
    Inventors: Volker Reber, Stefan Götz, Jari Rönfanz
  • Electrified vehicle and charging system
    Patent number: 10889193
    Abstract: An electrically-propelled vehicle includes a traction battery and a conductive charging pad disposed beneath the vehicle and electrically coupled to the battery. The charging pad is configured to transfer power from at least one contact extension disposed at a charge station to charge the battery. A height from ground of the charging pad is configured to cause electrical engagement of the contact extension as a result of the vehicle entering a parking space proximate the charge station.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: January 12, 2021
    Assignee: Ford Global Technologies, LLC
    Inventors: Christopher Robert Westfall, Rathi Kannan Munukur, Christopher W. Bell, John Paul Gibeau
  • Stretchable layout design for EUV defect mitigation
    Patent number: 10877370
    Abstract: A method for mitigating extreme ultraviolet (EUV) mask defects is disclosed. The method includes the steps of providing a wafer blank, identifying a first plurality of defects on the wafer blank, providing an EUV mask design on top of the wafer blank, identifying non-critical blocks with corresponding stretchable zones on the EUV mask design, overlapping the EUV blank with the EUV mask design, identifying a second plurality of defects, the second plurality of defects are solved, identifying a third plurality of defects, the third plurality of defects are not solved, adjusting the relative locations of the EUV mask design and the EUV blank to solve at least one of the third plurality of defects, and adjusting the locations of at least one of the non-critical blocks within corresponding stretchable zones to solve at least one of the third plurality of defects.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Lin Yang, Chin-Chang Hsu, Yen-Hung Lin, Chung-Hsing Wang, Wen-Ju Yang
  • Semiconductor device and method of manufacturing the same
    Patent number: 10872817
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises providing a layout comprising a first group that includes first and second patterns and a second group that includes third and fourth patterns, examining a bridge risk region in the layout, biasing one end of at least one of the first and third patterns, and forming first to fourth conductive patterns by respectively using the first to fourth patterns of the layout. The one end of at least one of the first and third patterns are adjacent to the bridge risk region.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daeho Yoon, Daeseon Jeon, Jaeyoung Choi
  • Intelligent switch system
    Patent number: 10873193
    Abstract: A charging path switching circuit includes a first port, a second port, a path switch unit, and a conversion unit. The first port is connected to an external electronic device to obtain a first electrical signal. The second port is connected to an external power source to obtain a second electrical signal. The conversion unit is connected the path switch unit and converts the first electrical signal or the second electrical signal to a predetermined voltage. The path switch unit is connected to the first port and the second port. The path switch unit selects to connect to the first port or the second port, to obtain the first electrical signal or the second electrical signal according to the connection of the first and the second port. The path switch unit preferentially selects to obtain the second electrical signal from the second port.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 22, 2020
    Assignee: AMBIT MICROSYSTEMS (SHANGHAI) LTD.
    Inventor: Yu-Hu Yan
  • Elmore delay time (EDT)-based resistance model
    Patent number: 10867097
    Abstract: We disclose an integrated circuit design tool for modeling resistance of a terminal of a transistor such as a gate, a source, a drain, and a via. A structure of the terminal is specified in a data structure in memory using a three-dimensional (3D) coordinate system. For each of a plurality of volume elements in the specified structure, an Elmore delay time (EDT) is determined. For those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, an average EDT (aEDT) is determined based on the EDT. Point-to-point resistance values of the terminal are generated as a function of the aEDT and a capacitance of the terminal.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 15, 2020
    Assignee: Synopsys, Inc.
    Inventor: Ralph Benhart Iverson
  • Methods and apparatus for monitoring a lithographic manufacturing process
    Patent number: 10866527
    Abstract: A method for monitoring a lithographic process, and associated lithographic apparatus. The method includes obtaining height variation data relating to a substrate supported by a substrate support and fitting a regression through the height variation data, the regression approximating the shape of the substrate; residual data between the height variation data and the regression is determined; and variation of the residual data is monitored over time. The residual data may be deconvolved based on known features of the substrate support.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: December 15, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Emil Peter Schmitt-Weaver, Kaustuve Bhattacharyya, Wim Tjibbo Tel, Frank Staals, Leon Martin Levasier
  • Simulation circuit and simulation method
    Patent number: 10866272
    Abstract: The object is to provide a technique for adjusting a turn-on operation and a turn-off operation of a transistor independently from each other in simulation for evaluating characteristics of the transistor. A simulation circuit for simulation for evaluating characteristics of a transistor includes a gate power supply configured to apply a voltage to a gate terminal of the transistor, a first diode connected between the gate terminal and the gate power supply, and a second diode connected in antiparallel with the first diode.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 15, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takahiro Nakatani, Katsumi Uryu, Tadaharu Minato
  • Method and apparatus for designing interconnection structure and method for manufacturing interconnection structure
    Patent number: 10860772
    Abstract: The present disclosure provides methods and apparatus for designing an interconnection structure and methods for manufacturing an interconnection structure, and relates to the technical field of semiconductors. An implementation of the method may include: designing n virtual interconnection units according to a number of metal interconnection layers in a circuit area of a chip design drawing, where an ith virtual interconnection unit includes i metal interconnection layers, and where adjacent metal interconnection layers in a jth virtual interconnection unit are connected by using vias, and n?2, 1?i?n, and 2?j?n; and filling an area in the chip design drawing outside the circuit area with virtual interconnection units, where the jth virtual interconnection unit is filled, and a (j?1)th virtual interconnection unit is not filled unless there is no space in the area for the jth virtual interconnection unit.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: December 8, 2020
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Duohui Bei
  • Side channel aware automatic place and route
    Patent number: 10860771
    Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: December 8, 2020
    Assignee: CHAOLOGIX, INC.
    Inventors: Subbayya Chowdary Yanamadala, Daniel F. Yannette, Brent Arnold Myers
  • Data processing engine (DPE) array global mapping
    Patent number: 10853541
    Abstract: Some examples described herein relate to global mapping of program nodes of a netlist of an application. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to obtain a netlist of an application. The netlist contains program nodes and respective edges between the program nodes. The application is to be implemented on a device comprising an array of data processing engines. The processor is also configured to execute the instruction code to generate a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generate a detailed mapping of the program nodes based on the global mapping; and translate the detailed mapping to a file.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: December 1, 2020
    Assignee: XILINX, INC.
    Inventors: Abhishek Joshi, Grigor S. Gasparyan, Aditya Chaubal, Sridhar Kirshnamurthy, Xiao Dong
  • Conversion of block model-based circuit designs into circuit implementations
    Patent number: 10846449
    Abstract: A design tool executing on a computer system converts a block model of a circuit design to a high-level language (HLL) specification. The design tool then converts the HLL specification to a hardware description language (HDL) specification. Circuit implementation data is generated from the HDL specification by the design tool, and the circuit implementation data can be used to make an integrated circuit that performs functions specified by the circuit design.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 24, 2020
    Assignee: Xilinx, Inc.
    Inventors: Avinash Somalinga Suresh, Nabeel Shirazi, Daniel E. Michek, Daniel G. Gibbons
  • Printed circuit board design
    Patent number: 10831939
    Abstract: For printed circuit board (“PCB”) design, methods, systems, and apparatuses are disclosed. One apparatus includes a component ID module that identifies a PCB component to be placed on a current board design; a search module that displays one or more instances of previous board designs containing the identified PCB component, wherein displaying the one or more instances of previous board designs containing the identified PCB component comprises displaying a region surrounding the identified PCB component; and an import module that imports a selected portion of a board design into the current board design from a selected one of the instances of previous board designs containing the identified PCB component.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Christo, David Green, Julio A. Maldonado, Diana D. Zurovetz
  • Integrated circuit design with optimized timing constraint configuration
    Patent number: 10831958
    Abstract: Generating a design of an integrated circuit by analyzing a physical design of an integrated circuit by determining, for a pin of a circuit of the integrated circuit, that a candidate timing constraint for signal arrival time at the pin is later than a current timing constraint for signal arrival time at the pin, determining that a slack value associated with the current timing constraint has a greater negative value than a predefined negative slack threshold value, determining that the current timing constraint is within a user-defined range of signal arrival time values associated with the pin, determining that the candidate timing constraint is earlier than a latest-allowable signal arrival time at the pin, setting the current timing constraint equal to the candidate timing constraint, and generating a revised physical design of the integrated circuit that incorporates the current timing constraint.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ofer Geva, Shiran Raz, Yaniv Maroz
  • Parallel power down processing of integrated circuit design
    Patent number: 10831938
    Abstract: Techniques for parallel power down processing of an integrated circuit (IC) design are described herein. An aspect includes receiving IC design information comprising a plurality of IC elements. Another aspect includes identifying a plurality of timing endpoints in the IC design information. Another aspect includes determining a plurality of nets, each net comprising a respective subset of the plurality of IC elements, based on the identified plurality of timing endpoints. Another aspect includes performing power down processing of net drivers in the plurality of nets, wherein the power down processing of at least a subset of the plurality of nets is performed in parallel.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jose Neves, Adam Matheny
  • Predicting routability of interconnects
    Patent number: 10831969
    Abstract: An integrated circuit physical design tool includes an interconnection congestion predictor that generates a congestion table for an integrated circuit design. Interconnection congestion hotspots are identified based on the congestion table. The proximity of interconnection congestion hotspots to each other is determined, and penalization values are computed based on the proximity of interconnection congestion hotspots to each other. The congestion table is then updated to reflect the penalization values due to proximity of interconnection congestion hotspots. Routability of the interconnection congestion hotspots is then predicted based on the updated congestion table. The updated congestion table may also be used by multiple physical design optimization tools, including placement, global routing, and detail routing.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Zhichao Li, Yaoguang Wei, Kai Liu, Manjunath Ravi, Su Liu
  • Interactive charging of battery-operated vehicles
    Patent number: 10807490
    Abstract: A method and associated computer program product and system are disclosed. The method comprises, while a battery-operated vehicle is not being charged by a power supply, receiving a first input at a user interface displayed on a computing device. The method further comprises, responsive to the first input, wirelessly transmitting a first control signal to the battery-operated vehicle to control motive operation thereof. The method further comprises, responsive to receiving an indication that the battery-operated vehicle is being charged by the power supply, displaying one or more tasks to be completed using the user interface. The method further comprises receiving a second input at the user interface while the one or more tasks are displayed, and responsive to the second input, wirelessly transmitting a second control signal to operate one or more output devices of the battery-operated vehicle.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: October 20, 2020
    Assignee: Disney Enterprises, Inc.
    Inventors: Corey D. Drake, Nicholas F. Barone, Clifford Wong, Jason A. Yeung, Michael P. Goslin
  • Integrated circuit layout wiring for multi-core chips
    Patent number: 10812079
    Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 20, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Chetan Bisht, Harry Scrivener, III
  • System and method for providing wireless power in a removable wireless charging module
    Patent number: 10797517
    Abstract: A wireless charging module includes an antenna and a wireless charger module. An enclosure is configured to fit at least partially within an optical drive bay of an information handling system. The antenna is disposed within a plastic lower portion of the enclosure. The plastic lower portion of the enclosure is configured to enable the antenna to wirelessly receive power from a wireless charging pad. The wireless charger module is disposed within the enclosure, and is configured to provide power to the information handling system.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 6, 2020
    Assignee: Dell Products, L.P.
    Inventors: Andrew T. Sultenfuss, Kevin W. Mundt
  • Compiler and hardware abstraction layer architecture for a neural network accelerator
    Patent number: 10789402
    Abstract: Examples herein describe a method for a compiler and hardware-abstraction-layer architecture for a programmable integrated circuit (IC). In one embodiment, a method for mapping and porting a neural network to an integrated circuit (IC) is disclosed. The method includes receiving a network description of the neural network; generating a framework independent network graph based on the network description; performing a plurality of back-end operations on the network graph to generate an execution sequence vector; and configuring the IC based on the execution sequence vector.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 29, 2020
    Assignee: XILINX, INC.
    Inventors: Kumar S. S. Vemuri, Abid Karumannil, Venkataraju Koppada, Anitha Barri, Anusha Perla, Vishal K. Jain, Sairam K. M. Menon, Anil K. Martha