Abstract: An information handling system with modular riser components for receiving expansion cards having various requirements. The system includes a riser body assembly having a common support structure for receiving expansion cards. The common support structure may be coupled to different expansion structures to provide support of expansion cards having requirements that would not be met by the common support structure alone.

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Abstract: Implementations of the present disclosure are directed to systems and methods for reducing design complexity and critical path timing challenges of credit return logic. A wide bus supports simultaneous transmission of multiple flits, one per lane of the wide bus. A source device transmitting flits on a wide bus selects from among multiple credit return options to ensure that only one of the multiple flits being simultaneously transmitted includes a credit return value. In some example embodiments, the receiving device checks only the flit of one lane of the wide bus (e.g., lane 0) for credit return data. In other example embodiments, the receiving device uses a bitwise-OR to combine the credit return data of all received flits in a single cycle.

Abstract: Methods and apparatus for processing signals captured by one or more sensors are disclosed. An example method includes receiving a first signal from a control circuit, the first signal including control data associated with the one or more sensors, recovering a fixed frequency clock signal and a control signal from the first signal, generating a spread spectrum clock signal based on the fixed frequency clock signal, receiving a sensor data signal based at least in part on data captured by the one or more sensors, the spread spectrum clock signal, and the control signal, retiming the sensor data signal based at least in part on the spread spectrum clock signal and the fixed frequency clock signal, and generating an output signal based on the retimed sensor data signal.

Abstract: The present disclosure discloses example operation accelerators and compression methods. One example operation accelerator performs operations, including storing, in a first buffer, first input data. In a second buffer, weight data can be stored. A computation result is obtained by performing matrix multiplication on the first input data and the weight data by an operation circuit connected to the input buffer and the weight buffer. The computation result is compressed by a compression module to obtain compressed data. The compressed data can be stored into a memory outside the operation accelerator by a direct memory access controller (DMAC) connected to the compression module.

Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.

Abstract: A bridging module, a data transmission system, and a data transmission method are provided. The bridging module obtains a first read request, and allocates a first data storage space for first return data corresponding to the first read request. The bridging module combines a first master transaction identifier and an address of the first data storage space as a first slave transaction identifier of the first read request, and sends the first read request to a slave device. The bridging module obtains a second read request, and allocates a second data storage space for second return data corresponding to the second read request. The bridging module combines a second master transaction identifier and an address of the second data storage space as a second slave transaction identifier of the second read request, and sends the second read request to the slave device.

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

Abstract: Systems and methods for direct memory control operations on memory data structures. In one implementation, a processing device receives, from a component of an application runtime environment, a request to perform a memory access operation on a portion of a memory space; determines a data structure address for a portion of a memory data structure, wherein the portion of the data structure is associated with the portion of the memory space; and performs, in view of the data structure address, the memory access operation directly on the portion of the memory data structure.

Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.

Abstract: The purpose of the present invention is to cause a reception side communication device to appropriately detect a start bit. A serial communication unit (100), which transmits serial data by a combination of a high level signal and a low level signal, is provided with: a serial communication part (111) that provides the start bit on the head of the serial data, and transmits the high level signal in a prescribed duration just before the start bit; and a duration setting part (113) that sets the duration.

Abstract: A first configurable address decoder can be coupled between a source node and a first interconnect fabric, and a second address decoder can be coupled between the first interconnect fabric and a second interconnect fabric. The first address decoder can be configured with a first address mapping table that can map a first set of address ranges to a first set of target nodes connected to the first interconnect fabric. The second address decoder can be configured with a second address mapping table that can map a second set of address ranges to a second set of target nodes connected to the second interconnect fabric. The second address decoder can be part of the first set of target nodes. The first address decoder and the second address decoder can be configured or re-configured to determine different routes for a transaction from the source node to a target node in the second set of target nodes via the first and second interconnect fabrics.

Abstract: A remote mapping method, apparatus and device for computing resources, and a storage medium, which are applied to a server. Said method comprises: identifying each FPGA heterogeneous accelerator card in an FPGA BOX; establishing a network communication connection with each FPGA heterogeneous accelerator card via a network interface of each FPGA heterogeneous accelerator card in the FPGA BOX, and establishing a network communication connection between FPGA heterogeneous accelerator cards; mapping each FPGA heterogeneous accelerator card to the server; establishing network transmission for the established network communication connections, and migrating a control flow and a data flow that are performed by the PCIE to the network transmission; and deploying a target application in the FPGA BOX through the established network transmission, and when running the target application, performing data exchange with the FPGA BOX via the network transmission.

Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.

Abstract: A signal processing chip includes a plurality of signal processing blocks each configured to transmit and receive a signal via a signal line, samples the signal on the signal line that is transmitted and received by the signal processing blocks, and transmits, to another signal processing chip, a data frame including information indicating the signal sampled at a timing of satisfying a predetermined condition.

Abstract: An apparatus that allows for access to any and all registers of a central processing unit in a line replaceable unit (LRU) without a need to open the housing of the LRU is provided. The apparatus may receive write or read packets from an external device and relay the same to an LRU. The apparatus may receive state information from one or more registers of the LRU in response. The apparatus may transmit or transfer the state information to an external device. The apparatus may be used to update firmware in the LRU, for diagnostics or testing.

Abstract: Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.

Abstract: A communication system includes a master unit; and a plurality of slave units including a slave unit to which a termination resistance is set, the plurality of slave units connected to the master unit via a communication line. In the communication system, the master unit includes a master communication control unit that normally sets a communication rate of communication performed with the plurality of slave units to a high baud rate, switches the high baud rate to a low baud rate after detecting that communication with the slave unit to which the termination resistance is set is disabled, transmits an instruction for switching the low baud rate to the high baud rate to the plurality of slave units after detecting that the communication with the slave unit to which the termination resistance is set is restored, and switches setting of the master unit itself to the high baud rate.

Abstract: A bus emulator device includes a first computer, a second computer, and an information interface. The first computer is configured to connect to a main bus system. The first computer includes at least write access into the information interface, and the second computer includes only read access into the information interface. In other aspects, the first computer includes only write access into the information interface, and the second computer includes at least read access into the information interface.

Abstract: A switching system includes a content-addressable memory (CAM) and several processing nodes. The CAM can be selectively connected to any one or more of the processing nodes during operation of the switching system, without having to power down or otherwise reboot the switching system. The CAM is selectively connected to a processing node in that electrical paths between the CAM and the processing nodes can be established, torn down, and re-established during operation of the switching system. The switching system can include a connection matrix to selectively establish electrical paths between the CAM and the processing nodes.