Abstract: A data storage device and method for lane selection based on thermal conditions are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to determine that action is needed to control a thermal state of the data storage device; and in response to determining that action is needed to control the thermal state of the data storage device, send a request to a host to reduce a number of lanes the host uses to communicate with the data storage device, wherein reducing the number of lanes reduces an amount of heat generated by the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A server rack has server sleds, each including a motherboard upon which is mounted: a memory module, a cache, at least one CPU connected to the cache, a memory controller connected to the cache and the memory module, an I/O hub, and a fabric interface (FIC) having a memory bridge and optical transceivers, where this memory bridge is connected to the I/O hub through this motherboard. The rack also has a memory sled disaggregated from the server sleds and that includes: a motherboard upon which is mounted: memory modules and a FIC having a memory bridge, a memory controller and optical transceivers, wherein this memory controller is connected to these memory modules through this motherboard, and wherein this memory bridge connects the memory controller to the optical transceivers. The rack has a photonic cross-connect switch interconnected by optical fiber cables to the optical transceivers of the server and memory sleds.

Abstract: A method and/or process of interface bridging device for providing a C physical layer (“C-PHY”) input output interface via a field programmable gate arrays (“FPGA”) is disclosed. The process, in one aspect, is capable of coupling a first wire of data lane 0 to a first terminal of first IO serializer of FPGA for receiving first data from a D-PHY transmitter of a first device and coupling a second wire of the data lane 0 to a second terminal of the first IO serializer of FPGA for receiving second data from the D-PHY transmitter. Upon activating a first scalable low-voltage signal to generate a first value on P channel and a second value on N channel in response to the first data and the second data, a first signal on first wire of trio 0 for a C-PHY output is generated based on the first value on the P channel.

Abstract: Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

Abstract: A system and method for storing data associated with a system management interrupt (SMI) in a computer system. Notification of a system management interrupt is received on a central processing unit. The central processing unit enters a system management mode. A system management handler of a basic input output system (BIOS) is executed by a bootstrap processor of the central processing unit. The system management interrupt is initiated via the bootstrap processor. The system management interrupt data is stored in a register of the bootstrap processor. The SMI data is converted to an accessible format. The converted SMI data is stored in a memory.

Abstract: Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains.

Abstract: A data network has at least three line branches connected via a common star node to distribute message signals from one of the line branches onto the other line branches, wherein connected to at least one of the line branches is at least one bus-user device is configured to generate in a corresponding transmit mode by a corresponding transmit unit at least one of the message signals, wherein in the corresponding bus-user device, the transmit unit has a current source circuit which, in generating the message signal (16), is configured to inject an electric current into electrical lines of the line branch to which the bus-user device is connected, and via the current source circuit the lines are connected to an internal impedance value of the current source circuit that in transmit mode is constantly greater than 10 times the value of the characteristic impedance, for example greater than 500 Ohms.

Abstract: A control unit architecture and a method in which a communication connection takes place between at least two control units, in particular in a vehicle. The method includes receiving the data packet by the first interface controller; determining, by a data analyzer, a transmission strategy for the data packet, the transmission strategy including at least one of the following actions: rejecting the data packet, and/or sending the data packet to at least one of the second interface controllers, and/or sending the data packet to at least one of the buffer stores, and/or fragmenting the data packet and sending it to at least one of the buffer stores, and/or sending the content of the at least one buffer store to at least one of the second interface controllers; implementing the transmission strategy for the data packet.

Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

Abstract: A circuit having multiple inputs and multiple outputs the circuit being for switching signals received at any of the inputs to any of the outputs, the circuit comprising: a first switch matrix, the first switch matrix being capable of directing signals received at the inputs of the circuit to multiple first intermediate ports; a second switch matrix, the second switch matrix being capable of directing signals received at multiple second intermediate ports to multiple third intermediate ports, the number of the second intermediate ports being less than the number of the inputs of the circuit; one or more primary bypass links, each primary bypass link being capable of coupling one or more of the first intermediate ports to a respective one or more of the outputs of the circuit independently of the second switch matrix; a first redirection layer, the first redirection layer being capable of, for each first intermediate port, directing a signal received at that first intermediate port to a primary bypass link or

Abstract: According to examples, an apparatus may include a processor that may access an assignment of a capability to a hardware port such as a Universal Serial Bus (“USB”) port. The apparatus may virtualize a USB port, assign capabilities to the virtual USB port, and provide electrical communication via the USB port subject to the assigned capabilities. The electrical communication may include power delivered via the USB port, or data communicated via the USB port.

Abstract: A GENZ port structure includes a body, a plurality of high-speed input pins, a plurality of high-speed output pins, a plurality of ground pins, a power supply pin, a plurality of differential clock pins, and a plurality of parameter setting pins. The main body includes a first side and a second side. The plurality of high-speed input pins are arranged on the first side. The plurality of high-speed output pins are arranged on the second side. The plurality of ground pins are interspersed between the plurality of high-speed input pins and the plurality of output pins. The power supply pins, the plurality of differential clock pins and the plurality of parameter setting pins are respectively arranged on one of the first side or the second side. The plurality of parameter setting pins are used to adjust an internal parameter setting of the GENZ port structure.

Abstract: A magnetic tape drive and an assembly for a tape drive are disclosed herein. The disclosed magnetic tape drive comprises a SAS-compliant tape drive module; and a USB-C to SAS assembly having one or more controllers operatively coupled to a USB-C connector and a SAS connector. The SAS connector of the USB-C to SAS assembly is operatively coupled to the SAS-compliant tape drive module. The USB-C to SAS assembly is configured to enable the magnetic tape drive to interface a USB-C-compliant computing device with the SAS-compliant tape drive module, and the USB-C to SAS assembly is configured to transmit tape commands received at the USB-C connector to the SAS-compliant tape drive module via the one or more controllers and the SAS connector. The assembly includes a SAS connector, a USB-C connector, and one or more controllers operatively coupled to the SAS connector and the USB-C connector.

Abstract: A method for providing teleportation services includes receiving, by a computing device, a first signal. The first signal indicates a request for a teleportation event between a first quantum computing system (QCS) and a second QCS. A first set of qubits is associated with the first QCS. A second set of qubits is associated with the second QCS. In response to receiving the first signal, the computing device causes an allocation of a first qubit of the first set of qubits for the teleportation event. In response to receiving the signal, the computing device causes an allocation of a second qubit of the second set of qubits for the teleportation event. The computing device receives a second signal that indicates a successful completion of the teleportation event. In response to receiving the second signal, the computing system causes a deallocation of the first qubit of the first set of qubits.

Abstract: In an example in accordance with the present disclosure, a system is described that includes a hub for routing data traffic between a first computing device and a second computing device. A detection device of the system detects a communication protocol between the computing devices. A switch of the system routes traffic directly between the computing devices when a first communication protocol is detected. When a second communication protocol is detected, the switch re-routes traffic of the first type from the first computing device back to the hub to convert the traffic of the first type to a second type and routes converted traffic directly to the second computing device.

Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

Abstract: The present disclosure relates to packing transaction layer (TL) packets at a link layer of a protocol stack. In some examples, channel type data identify a type of message channel for a first TL packet can be generated. A set of slot formats for a slot for packing the first TL packet can be identified based on the channel type data and a slot format database. A respective slot format of the set of slot formats can be selected for the slot based on a message type of the first TL packet, and a message type of a second TL packet. The first TL packet and the second TL packet can be packed into the slot having the selected respective slot format during generation of a link layer packet.

Abstract: An asynchronous first device in communication with an asynchronous second device. The time for the first device to complete a processing cycle is a first device major frame and the first device major frame comprises a first device dedicated processing time slot at the end of the first device major frame. The first device is configured to send a rescheduling signal to the second device when it has completed a first device major frame. The first device is configured, during every first device dedicated processing slot, to: monitor for a rescheduling signal sent from the second device to the first device; and if a rescheduling signal from the second device is received: reschedule the current first device major frame to a rescheduled first device major frame; wherein the end of the rescheduled first device major frame coincides with the time the rescheduling signal from the second device was received.

Abstract: Methods and apparatuses directed to more efficient data transfers within die architectures. In some examples, a die package includes controller logic electrically coupled to a first communication bus and a second communication bus. The controller logic can receive an initial data transfer request over the first communication bus, and determine a final address of the initial data transfer request. Further, the controller logic can assert a chip select signal of the second communication bus to initiate a data exchange. While asserting the chip select signal, the controller logic can receive an additional data transfer request over the first communication bus, and determine an initial address of the additional data transfer request. Based on the determined initial and final addresses, the controller logic can initiate an additional data exchange over the second communication bus without de-asserting the chip select signal.