Abstract: Configurable binary circuits for use in electrical power systems may include an input/output port, a binary input subsystem for receiving a binary input signal, a binary output subsystem for transmitting a binary output signal, and a switch subsystem for selecting one of the binary input subsystem or the binary output subsystem for operation. Intelligent electronic devices (IEDs) and associated methods may include one or more configurable binary circuits.

Abstract: An electronic device includes a slave interface configured for coupling to a machine controller of a machine via a multi-drop bus (MDB), a host interface configured for coupling to a first peripheral device of the machine, and memory storing one or more programs to be executed by the one or more processors and comprising instructions for: registering the electronic device as a slave to the machine controller, registering the first peripheral device as a slave to the electronic device, receiving from a mobile device a request to access signals generated by the first peripheral device, validating the request, and sending a reset command to the first peripheral device via the host interface, the reset command including a directive to update a signal destination address of the first peripheral device from a controller address of the machine controller to a device address of the electronic device.

Abstract: Data exchanges between an ultra-wide band communication module and a secure element are controlled such that the data exchanges pass through a near-field communication router. The near-field communication router controls routing of the data exchanges so that the data exchanges do not pass through a host circuit that is also coupled to the near-field communication router.

Abstract: An electronic device includes a CPU, an acceleration module, and a memory. The acceleration module is communicatively connected with the CPU, and includes chips. The chip according to an embodiment includes a data bus, and a memory, a data receiver, a computing and processing unit, and a data transmitter connected to the data bus. The data receiver receives first data and header information from outside, writes the first data to a corresponding area of the memory through the data bus, and configures a corresponding computing and processing unit and/or data transmitter according to the header information. The computing and processing unit receives first task information, performs an operation processing according to the first task information and a configuration operation on the data transmitter. The data transmitter obtains second task information and second data, and outputs third data to outside based on at least part of the second data.

Abstract: One embodiment of the present invention discloses a two-phase configuration process (“TCP”) to configure a field-programmable gate array (“FPGA”) to include a configurable microcontroller unit (“CMU”) during a phase I configuration and configuring the CMU during a phase II configuration. TCP, in one aspect, is able to receive first configuration data from a first external storage location via a communication bus. After storing the first configuration data in a first configuration memory for configuring FPGA to contain a CMU for the phase I configuration, second configuration data with MCU attributes is obtained from a second external storage location via the communication bus. The second configuration data is subsequently stored in a second configuration memory for programming the CMU for the phase II configuration.

Abstract: The present disclosure advantageously provides a method and system for transferring data over a chip-to-chip interconnect (CCI). At a request node of a coherent interconnect (CHI) of a first chip, receiving at least one peripheral component interface express (PCIe) transaction from a PCIe master device, the PCIe transaction including a stream identifier; selecting a CCI port of the CHI of the first chip based on the stream identifier of the PCIe transaction; and sending the PCIe transaction to the selected CCI port.

Abstract: An optical output device is described that includes one bus system. The bus system includes two bus wires of a bus, two bus units and one bus control unit. The two bus units may include one optical output element one output control unit whose output is connected to the one optical output element a first storage unit for storing address data of the respective bus unit a second storage unit for storing a counter value, a comparison unit whose inputs are connected to the first storage unit and to the second storage unit, and a control unit whose input is connected to an output of the comparison unit and which controls the takeover of data from the bus into the output control unit depending on an output signal or on output data of the comparison unit.

Abstract: Systems are provided where a chassis houses an Information Handling System (IHS). The chassis includes a motherboard with one or more CPUs configured to operate as a root complex for a PCIe switch fabric that includes a plurality of PCIe devices of the IHS. The chassis also includes an I/O module providing I/O capabilities for the motherboard. The I/O module includes a network controller configured to allocate network bandwidth for use by a hardware accelerator sled installed in the chassis, unless an integrated network controller is detected as a component of a hardware accelerator baseboard installed in the hardware accelerator sled. The I/O module also includes a PCI switch configured to operate with the CPUs as the root complex of the PCIe switch fabric and further configured to operate with the hardware accelerator baseboard as the root complex of the PCIe switch fabric.

Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

Abstract: A USB active optical cable and a plug capable of managing power consumption and state. The USB active optical cable and plug respectively comprises a first plug, a second plug, and an optical transmission medium used to connect the first plug and the second plug; the first plug and the second plug are configured to operate different operating states, including an initialization mode, a transmission mode, and a power saving mode, and they can switch between the different operating states. The USB active optical cable and plug are both based on the separate control of the transmitting unit and the receiving unit to distinguish different operating modes, provide necessary operating requirements and mode switching conditions for each mode, and also enable the checking and transmission of the plugging state in the power saving mode, thus facilitate the power consumption management of the active optical cable.

Abstract: A surgical instrument is disclosed. The surgical instrument includes a first control circuit configured to communicate with an energy module using at least a first protocol over a first communication line and a second control circuit configured to communicate with another surgical instrument coupled to the surgical instrument using at least a second protocol over a second communication line.

Abstract: A data interconnect system includes: a plurality of pins arranged within a receptacle, a first one of the pins being a power pin, wherein the pins are electrically isolated from each other within the receptacle; a first switching network including a first plurality of parallel switching devices, each of the parallel switching devices of the first plurality of parallel switching devices coupling a respective one of the pins to a node; a first current path from the node to ground, the first current path including a current device; and a second current path, parallel to the first current path, the second current path including a resistor coupling the node to ground.

Abstract: A data storage device and method for lane detection and configuration are provided. In one embodiment, a data storage device is provided comprising a memory, an interface, and a controller. The controller is configured to detect whether a cable coupled with the interface is providing a first channel configuration signal that indicates that the cable is in a first cable orientation or a second channel configuration signal that indicates that the cable is in a second cable orientation. In response to detecting that the cable is not providing either the first or the second channel configuration signal, the controller uses a default lane configuration to communicate with the host via the cable. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: An integrated circuit is described. This integrated circuit may include: an interface module with a first power domain and a second power domain. The first power domain may include a digital controller, and the second power domain may include a first analog front end (AFE) circuit. Moreover, the interface module may include up/down level shifters that communicate electrical signals that include a DC component from the first power domain to the second power domain. In some embodiments, the integrated circuit may provide a fully on-chip solution to handle level shifting between the AFE circuit and a digital controller in Universal Serial Bus (USB) 2.0 during communication of electrical signals in a full-speed mode and/or a high-speed mode.

Abstract: A connector connection verification system includes a cable connector and a networking device. The networking device includes a port system defining a port and including a networking device connector, and at least one cable connector sensor device that is located adjacent the port. The cable connector sensor device(s) detects that the cable connector is inserted in the port defined by the port system while the cable connector does not mate with the networking device connector included in the port system and, in response, transmits an incorrect connection signal that indicates that the cable connector is incorrectly connected to the port system. A management interface provided on the networking device may receive the incorrect connection signal from the cable connector sensor device(s), and provide information that describes the cable connector and that indicates that the cable connector is incorrectly connected to the port system for display on a display device.

Abstract: A method includes, responsive to receiving a modified first reservation command from a storage controller, identifying, by a storage drive, a first range of storage based on a first range identifier of the modified reservation command. The method also includes granting, by the storage drive, a reservation for access to the storage drive on behalf of a first host controller by associating the reservation for the first range with a second range of storage.

Abstract: A system and method of docking an information handling system to an intelligent wireless fan dock comprising a docking sensor to detect a docking event, a wireless module to establish a wireless link of the intelligent wireless fan dock with the docked information handling system upon detection of a docking event and to receive a dynamic fan speed request command to adjust extended fan cooling airflow from fan dock control system operating at the docked information handling system, where the fan dock control system has determined that the docked information handling system and the intelligent wireless fan dock pairing enables an increased performance mode and altered power draw limitations for the docked information handling system relative to the information handling system in an undocked state, and increasing the extended fan cooling airflow of a cooling fan based on the dynamic fan speed request command from the docked information handling system.

Abstract: The present disclosure includes a control board including a switchable input/output port. The switchable I/O port may provide a switchable communication bus capable of selectively supporting one of multiple different communication protocols and may provide a switchable power bus capable of selectively conducting electrical power from one of multiple different power supplies. As such, the control board may communicatively and/or electrically couple to a wide range of devices. To that end, the control board may support the dynamic interchange and reconfiguration of devices coupled to the control board, allowing a control system including the control board greater operational flexibility.

Abstract: Communication fabric-coupled computing architectures, platforms, and systems are provided herein. In one example, an apparatus includes a management entity configured to establish a compute unit comprising components from among a plurality of physical computing components by at least instructing a communication fabric communicatively coupling the plurality of physical computing components to establish logical isolation within the communication fabric to form the compute unit. Responsive to an indication of a change in workload associated with at least a software component deployed to a processing element of the compute unit, the management entity is configured to adjust the logical isolation to alter a quantity of the plurality of physical computing components in the compute unit in accordance with the change in the workload.

Abstract: An equalization time configuration method is applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used. The equalization time configuration method includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.