Abstract: A bridging module, a data transmission system, and a data transmission method are provided. The bridging module obtains a first read request, and allocates a first data storage space for first return data corresponding to the first read request. The bridging module combines a first master transaction identifier and an address of the first data storage space as a first slave transaction identifier of the first read request, and sends the first read request to a slave device. The bridging module obtains a second read request, and allocates a second data storage space for second return data corresponding to the second read request. The bridging module combines a second master transaction identifier and an address of the second data storage space as a second slave transaction identifier of the second read request, and sends the second read request to the slave device.

Abstract: The present disclosure discloses example operation accelerators and compression methods. One example operation accelerator performs operations, including storing, in a first buffer, first input data. In a second buffer, weight data can be stored. A computation result is obtained by performing matrix multiplication on the first input data and the weight data by an operation circuit connected to the input buffer and the weight buffer. The computation result is compressed by a compression module to obtain compressed data. The compressed data can be stored into a memory outside the operation accelerator by a direct memory access controller (DMAC) connected to the compression module.

Abstract: The purpose of the present invention is to cause a reception side communication device to appropriately detect a start bit. A serial communication unit (100), which transmits serial data by a combination of a high level signal and a low level signal, is provided with: a serial communication part (111) that provides the start bit on the head of the serial data, and transmits the high level signal in a prescribed duration just before the start bit; and a duration setting part (113) that sets the duration.

Abstract: A remote mapping method, apparatus and device for computing resources, and a storage medium, which are applied to a server. Said method comprises: identifying each FPGA heterogeneous accelerator card in an FPGA BOX; establishing a network communication connection with each FPGA heterogeneous accelerator card via a network interface of each FPGA heterogeneous accelerator card in the FPGA BOX, and establishing a network communication connection between FPGA heterogeneous accelerator cards; mapping each FPGA heterogeneous accelerator card to the server; establishing network transmission for the established network communication connections, and migrating a control flow and a data flow that are performed by the PCIE to the network transmission; and deploying a target application in the FPGA BOX through the established network transmission, and when running the target application, performing data exchange with the FPGA BOX via the network transmission.

Abstract: A signal processing chip includes a plurality of signal processing blocks each configured to transmit and receive a signal via a signal line, samples the signal on the signal line that is transmitted and received by the signal processing blocks, and transmits, to another signal processing chip, a data frame including information indicating the signal sampled at a timing of satisfying a predetermined condition.

Abstract: A switching system includes a content-addressable memory (CAM) and several processing nodes. The CAM can be selectively connected to any one or more of the processing nodes during operation of the switching system, without having to power down or otherwise reboot the switching system. The CAM is selectively connected to a processing node in that electrical paths between the CAM and the processing nodes can be established, torn down, and re-established during operation of the switching system. The switching system can include a connection matrix to selectively establish electrical paths between the CAM and the processing nodes.

Abstract: A communication system includes a master unit; and a plurality of slave units including a slave unit to which a termination resistance is set, the plurality of slave units connected to the master unit via a communication line. In the communication system, the master unit includes a master communication control unit that normally sets a communication rate of communication performed with the plurality of slave units to a high baud rate, switches the high baud rate to a low baud rate after detecting that communication with the slave unit to which the termination resistance is set is disabled, transmits an instruction for switching the low baud rate to the high baud rate to the plurality of slave units after detecting that the communication with the slave unit to which the termination resistance is set is restored, and switches setting of the master unit itself to the high baud rate.

Abstract: Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.

Abstract: A bus emulator device includes a first computer, a second computer, and an information interface. The first computer is configured to connect to a main bus system. The first computer includes at least write access into the information interface, and the second computer includes only read access into the information interface. In other aspects, the first computer includes only write access into the information interface, and the second computer includes at least read access into the information interface.

Abstract: An apparatus that allows for access to any and all registers of a central processing unit in a line replaceable unit (LRU) without a need to open the housing of the LRU is provided. The apparatus may receive write or read packets from an external device and relay the same to an LRU. The apparatus may receive state information from one or more registers of the LRU in response. The apparatus may transmit or transfer the state information to an external device. The apparatus may be used to update firmware in the LRU, for diagnostics or testing.

Abstract: A universal serial bus (USB) hub with a host bridge function and a control method thereof are provided. The USB hub utilizes a host bridge controller to connect two upstream ports so that two host devices connected to the two upstream ports are capable of transmitting/receiving data each other synchronously, thereby increasing usage convenience and flexibility and making full use of the tow upstream ports.

Abstract: A data network has at least three line branches connected via a common star node to distribute message signals from one of the line branches onto the other line branches, wherein connected to at least one of the line branches is at least one bus-user device is configured to generate in a corresponding transmit mode by a corresponding transmit unit at least one of the message signals, wherein in the corresponding bus-user device, the transmit unit has a current source circuit which, in generating the message signal (16), is configured to inject an electric current into electrical lines of the line branch to which the bus-user device is connected, and via the current source circuit the lines are connected to an internal impedance value of the current source circuit that in transmit mode is constantly greater than 10 times the value of the characteristic impedance, for example greater than 500 Ohms.

Abstract: The application discloses a terminal and a Type C interface anti-corrosion method. In the terminal, a processor is separately connected to a motion sensor and an interface chip. The interface chip is separately connected to the processor and a CC pin in a first Type C interface. The motion sensor is configured to monitor a motion status of the terminal, and the processor is configured to control, according to the motion status of the terminal, the interface chip to configure the CC pin of the first Type C interface to be in a low-level mode when it is determined that the motion status of the terminal changes from a moving state to a static state. When the motion status of the terminal changes from the moving state to the static state, the change in the motion status of the terminal is that the terminal is disconnected from an external device.

Abstract: A method for programming and controlling of a plurality of slave devices serially connected in a daisy chain configuration using a master device includes assigning a unique slave address to each slave device in the plurality of slave devices by sending an initialization data packet from the master device serially through the plurality of slave devices; storing, in each of the plurality of slave devices, the assigned slave address; defining a data packet; and transmitting the data packet serially to one or more of the plurality of slave devices. The data packet has a target slave address, a read/write command, a start address, and optionally a register address and an increment value.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device includes a transaction layer generating a transaction packet for transmission of a transaction, a data link layer generating a link packet including a protection code and a sequence number for the transaction packet and a link packet including a sequence number on the basis of the transaction packet, a physical layer generating a physical packet on the basis of the link packet and sequentially outputting the physical packet, a link training module performing negotiation for a link coupled through the physical layer and maintaining data information based on whether a link down occurring when the negotiation for the link is not performed is requested by a host or not, and a PCIe register storing information about the transaction layer, the data link layer, the physical layer, and the link training module.

Abstract: A computerized system operating in conjunction with computerized apparatus and with a fabric target service in data communication with the computerized apparatus, the system comprising functionality residing on the computerized apparatus, and functionality residing on the fabric target service, which, when operating in combination, enable the computerized apparatus to coordinate access to data.

Abstract: The technology described herein is directed towards reducing resource-related messages in a distributed locking system in which exclusive locks can be granted. Requests for a resource lock or range thereof received during an interval are queued, along with lock release messages. The queue is processed after the interval to update the resource state, which can result in a reduction in messages. In one example, separate lock request messages received during an interval from the same requestor for two or more consecutive resource ranges are combined, whereby a single lock grant message for the combined resource ranges is sent instead of one for each request. In another example, if in an interval a lock request for a resource/range is received before a lock release, the lock is released before the lock request message is processed. This avoids sending a lock release request message to the previous owner.

Abstract: A network interface module for coupling a host device to a switched network as a network node is described. The network interface module comprises a single half-duplex port for communicatively coupling to a shared bus of the switched network, at least one frame queue sized to store one multicast read frame received via the shared bus, and logic circuitry. The logic circuitry is configured to decode a read command for the interface module included in a payload of the multicast read frame that includes multiple read commands for other network nodes of the switched network, and transmit a response frame including read data on the shared bus when detecting the shared bus is available for transmitting.

Abstract: A user station for a serial bus system and a method for communication in a serial bus system. The user station includes an application for carrying out a task, a transceiver unit for serially receiving a message in the form of a frame from a bus of the bus system, via which user stations of the bus system exchange messages with one another, and a filter module for filtering the received frame. The filter module for filtering is designed to check at least two segments of the frame separately to determine whether or not the received frame is to be passed on to the application.

Abstract: There are provided a substrate; a main body case; and a first locking member and a second locking member for fixing the substrate and the main body case, the substrate includes a first receptacle connector configured to be coupled to a first plug of a first cable, a second receptacle connector configured to be coupled to a second plug of a second cable, a first coil that supplies electric power to the first receptacle connector, and a second coil that supplies electric power to the second receptacle connector, a distance from the first locking member to the first coil is shorter than a distance from the first locking member to the first receptacle connector, and a distance from the second locking member to the second coil is shorter than a distance from the second locking member to the second receptacle connector.