Abstract: Some embodiments include a stand that includes a communication interface, a universal serial bus (USB) microcontroller, and one dual purpose RJ12 interface configured to switch between a cash drawer mode and an RS232 mode. The stand can be configured to be coupled to a main display device. The main display device (e.g., an application running on the main display device) can enable selection of the cash drawer mode for communications via the dual purpose RJ12 interface, and receive an input signal after the selection. The main display device can enable selection of the RS232 mode for communications via the dual purpose RJ12 interface based on the input signal and transmit an indication to the stand, where the dual purpose RJ12 interface is configured to operate in the RS232 mode. The stand can include a hinge structure that enables the main display device to be flipped to face an opposite direction.

Abstract: Techniques are disclosed for managing the connection assignments of a plurality of accessory devices to one or more hub devices. In one example, a user device acting as a leader device receives an assignment request from an accessory device. The user device may obtain information corresponding to hub attributes from the one or more hub devices. The user device may also obtain accessory traits from the accessory device. The user device can compare the accessory traits with the hub attributes to determine a connection score for each hub device. The user device can then assign the accessory device to the hub device with the highest connection score.

Abstract: A data processing apparatus is provided, that includes communication configured for receiving, from an origin Peripheral Component Interconnect Express (PCIe) device, a translated PCIe packet comprising a destination field that comprises a physical address of a destination PCIe device. Permission circuitry transmits a permission check packet, separate to the translated PCIe packet, to a root port to determine whether the origin PCIe device has permission to access the destination PCIe device. Buffer circuitry stores the translated PCIe packet until a response to the permission check packet is received.

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

Abstract: An electronic device comprising: a clock pin; at least one data pin; a storage device, configured to store at least one program; a processing circuit, coupled to the clock pin and the data pin. A device ID setting method is performed when the processing circuit executes the program stored in the storage device. The device ID setting method comprises; (a) recording connections between pins between the first electronic device and the second electronic device by the second electronic device; (b) applying the connections as a device ID of the first electronic device by the second electronic device; and (c) setting pins of the first electronic device such that the data pins of the second electronic device are coupled to the data pins of the first electronic device.

Abstract: According to an embodiment, an electronic device comprises: a connecting terminal; a memory; and a processor connected to the connecting terminal and the memory, wherein the processor is configured to: identify a head unit of a vehicle connected to the connecting terminal; obtain information about a model of a vehicle or an installed operating system, associated with the identified head unit; and when the information about a specified tuning value for the identified head unit is stored in the memory, tune a register by using the specified tuning value.

Abstract: In example implementations, a computing device is provided. The computing device includes an expansion interface, a first device, a second device, and a processor communicatively coupled to the expansion interface. The expansion interface includes a plurality of slots. Two slots of the plurality of slots are controlled by a single reset signal. The first device is connected to a first slot of the two slots and has a feature that is compatible with the single reset signal. The second device is connected to a second slot of the two slots and does not have the feature compatible with the single reset signal. The process is to detect the first device connected to the first slot and the second device connected to the second slot and disable the feature by preventing the first slot and the second slot from receiving the single reset signal.

Abstract: In certain aspects, a memory device includes a memory string including a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory string. The peripheral circuit is configured to in response to an interrupt during a program operation on a select memory cell of the plurality of memory cells, turn on at least one of the DSG transistor or the SSG transistor. The peripheral circuit is also configured to suspend the program operation after turning on the at least one of the DSG transistor or the SSG transistor.

Abstract: A method includes receiving, at a first computing device, a first input/output (IO) command from a first artificial intelligence processing unit (AI PU), the first IO command associated with a first AI model training operation. The method further includes receiving, at the first computing device, a second IO command from a second AI PU, the second IO command associated with a second AI model training operation. The method further includes assigning a first timestamp to the first IO command based on a first bandwidth assigned to the first AI model training operation. The method further includes assigning a second timestamp to the second IO command based on a second bandwidth assigned to the second AI model training operation.

Abstract: The present invention describes a method for data transmission between an integrated circuit and an evaluation unit connected to an interrupt pin of the integrated circuit, characterized in that the data transmission is carried out by selectively triggering an atypical interrupt signal or a plurality of interrupt signals composed of regular and/or atypical interrupt signals.

Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

Abstract: Data processing apparatuses, methods of data processing, complementary instructions and programs related to ring buffer administration are disclosed. An enqueuing operation performs an atomic compare-and-swap oper-ation to store a first processed data item indication to an enqueuing-target slot in the ring buffer contingent on an in-order marker not being present there and, when successful, determines that a ready-to-dequeue condition is true for the first processed data item indication. A dequeuing operation, when the ready-to-de-queue condition for a dequeuing-target slot is true, comprises writing a null data item to the dequeuing-target slot and, when dequeuing in-order, further comprises, dependent on whether a next contiguous slot has null content, determining a retirement condition and, when the retirement condition is true, performing a retirement process on the next contiguous slot comprising making the next con-tiguous slot available to a subsequent enqueuing operation.

Abstract: An apparatus for a quantum computer comprising a memory device and a converter block, the memory device comprising: a local command module; and a double-buffer-memory module comprising a plurality of pairs of memory modules, each memory module: coupled to the local command module; and configured to store a respective operation for controlling a qubit of the quantum computer; wherein the local command module is configured to: receive an instruction to provide the operation for the qubit; read the operation from a respective one of the plurality of pairs of memory modules indicated by the instruction; and provide the operation to the converter block; wherein the converter block is configured to receive the operation from the memory device and provide digital output pulses, representative of the operation, to an output interface, the output interface configured to provide the digital output pulses to a digital-to-analogue converter for controlling the qubit to perform the operation.

Abstract: A method for timestamping and synchronization with high-accuracy timestamps in low-power sensor systems is provided. The method is performed by a device and includes: receiving, by a sensor hub of the device, an interrupt signal from a sensor and performing an interrupt service routine (ISR) to obtain an interrupt timestamp obtained by a latch, wherein the interrupt timestamp is obtained from an always-running unified time reference; obtaining, by the sensor hub, sensor data from the sensor; predicting, by the sensor hub, a prediction timestamp based on an amount of sensor data and the interrupt timestamp by using a filtering algorithm; and correcting, by the sensor hub, a timestamp of each sensor data based on the prediction timestamp.

Abstract: Excessive polling that may result in wasted computing resources and unnecessary network traffic can be avoided using some techniques described herein. In one example, a method can include obtaining historical data indicating execution times associated with computing operations. The method can also include determining polling times to assign to the computing operations by applying a model to the historical data. The method may also include configuring a software application to implement the polling times in relation to polling processes for transmitting requests to execute the computing operations to one or more destinations.

Abstract: Sideband signaling in Universal Serial Bus (USB) Type-C communication link allows multiple protocols that are tunneled through a USB link, where sideband signals may be provided through the sideband use (SBU) pins. Further, the SBU pins may be transitioned between different modes of sideband signals. In particular, signals in an initial mode may indicate a need or desire transition to a second mode. After a negotiation, linked devices agree to transition, the two devices may transition to the second mode. By providing this inband sideband signaling that allows mode changes, more protocols can be tunneled with accompanying sideband signaling and flexibility of the USB link is expanded.

Abstract: Described are methods for configuring computing system for and computing systems for PCIe communication between remote computing assets. The system uses a fabric interface device configured to receive multi-lane serial PCIe data from functional elements of a computing asset through a multi-lane PCIe bus, and to transparently extend the multi-lane PCIe bus by converting the multi-lane PCIe data into a retimed parallel version of the PCIe multi-lane data to be sent on bidirectional data communication paths. The fabric interface device is also configured so that the multi-lane PCIe bus can have a first number of lanes and the bidirectional data communication paths can have a different second number of lanes.

Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

Abstract: Methods and systems are provided for implementing a streaming deficit round robin arbiter to provide fair utilization of a single link. In some aspects, methods and systems are provided and can include specifying a quantum size indicating how much of a link of a stream is available for use, adding the quantum size to a deficit counter indicating available bandwidth, determining whether to provide a first data packet to an autonomous vehicle system based on the deficit counter and without determining a data packet size of the first data packet, and providing the first data packet to the autonomous vehicle system based on the determining of whether to provide the first data packet to the autonomous vehicle system.

Abstract: The present disclosure is directed to an input/output module.