Patents Examined by Hsin-Yi Hsieh
-
Patent number: 11404432Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.Type: GrantFiled: December 6, 2019Date of Patent: August 2, 2022Assignee: SK hynix Inc.Inventors: Hye-Hyeon Byeon, Sang-Deok Kim, Il-Young Kwon, Tae-Hong Gwon, Jin-Ho Bin
-
Patent number: 11393856Abstract: An image sensing device capable of minimizing reflection of light incident upon a metal layer is disclosed. The image sensing device includes a semiconductor substrate in which at least one groove is formed, a reflection prevention layer formed over the semiconductor substrate in a manner that the at least one groove is buried by the reflection prevention layer, and a metal layer formed over the reflection prevention layer, and provided with at least one through-hole corresponding to the at least one groove.Type: GrantFiled: April 15, 2019Date of Patent: July 19, 2022Assignee: SK hynix Inc.Inventor: Woo Yung Jung
-
Patent number: 11393952Abstract: The array of gallium-nitride (GaN) nanocolumns have quantum wells in a polar c-plane or in a semi-polar plane to emit light directed to ends of the nanocolumns and an interstitial filler material with light emitted in the nanocolumns being guided to exit from an end of the nanocolumns.Type: GrantFiled: January 18, 2022Date of Patent: July 19, 2022Inventors: Najeeb Ashraf Khalid, Huy Binh Le, Alexander Novikov
-
Patent number: 11393904Abstract: The nitride-based semiconductor device includes a carrier traveling layer 1 composed of non-doped AlXGa1-XN (0?X<1); a barrier layer 2 formed on the carrier traveling layer 1 and composed of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the carrier traveling layer 1; a threshold voltage control layer 3 formed on the barrier layer 2 and composed of a non-doped semiconductor having a lattice constant equal to that of the carrier traveling layer 1; and a carrier inducing layer 4 formed on the threshold voltage control layer 3 and composed of a non-doped or n-type semiconductor having a lattice constant smaller than that of the carrier traveling layer 1. The nitride-based semiconductor device further includes a gate electrode 5 formed in a recess structure, a source electrode 6 and a drain electrode 7.Type: GrantFiled: September 11, 2019Date of Patent: July 19, 2022Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Masahiko Kuraguchi
-
Patent number: 11393693Abstract: A structure manufacturing method including: preparing a treatment object that includes an etching target having a surface to be etched comprising a conductive group III nitride and a region to be etched, a conductive member in contact with at least a portion of a surface of a conductive region of the etching target that is electrically connected to the region to be etched, and a mask formed on the surface to be etched and comprising a non-conductive material; and etching the group III nitride by immersing the treatment object in an alkaline or acidic etching solution containing peroxodisulfate ions as an oxidizing agent that accepts electrons, and irradiating the surface to be etched with light through the etching solution, wherein an edge that defines the region to be etched is constituted by an edge of the mask without including an edge of the conductive member.Type: GrantFiled: March 13, 2020Date of Patent: July 19, 2022Assignees: SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Fumimasa Horikiri, Noboru Fukuhara
-
Patent number: 11362087Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.Type: GrantFiled: July 30, 2018Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Wen Liu, Chao-Hsiung Wang
-
Patent number: 11348789Abstract: A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having first and second sides; forming at least one doping region at the first side; forming a first metallization structure at the first side on and in contact with the at least one doping region; and subsequently forming a second metallization structure at the second side, the second metallization structure forming at least one silicide interface region with the semiconductor substrate and at least one non-silicide interface region with the semiconductor substrate.Type: GrantFiled: August 18, 2020Date of Patent: May 31, 2022Assignee: Infineon Technologies AGInventor: Jochen Hilsenbeck
-
Patent number: 11342477Abstract: A method of making a semiconductor device, comprising: forming a plurality of semiconductor seeds of a first III-nitride material through a mask provided over a substrate; growing a second III-nitride semiconductor material; planarizing the grown second semiconductor material to form a plurality of discrete base elements having a substantially planar upper surface. Preferably the step of planarizing involves performing atomic distribution of III type atoms of the grown second semiconductor material under heating to form the planar upper surface, and without supply of III type atoms is carried out during the step of planarization.Type: GrantFiled: February 13, 2017Date of Patent: May 24, 2022Assignee: HEXAGEM ABInventors: Lars Samuelson, Jonas Ohlsson, Zhaoxia Bi
-
Patent number: 11335838Abstract: A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer.Type: GrantFiled: January 23, 2018Date of Patent: May 17, 2022Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.Inventors: Kwang Ki Choi, Hwan Hee Jeong, Sang Youl Lee, June O Song
-
Patent number: 11329026Abstract: Apparatuses and methods for internal heat spreading for packaged semiconductor die are disclosed herein. An example apparatus may include a plurality of die in a stack, a bottom die supporting the plurality of die, a barrier and a heat spreader. A portion of the bottom die may extend beyond the plurality of die and a top surface of the bottom die extending beyond the plurality of die may be exposed. The barrier may be disposed alongside the plurality of die and the bottom die, and the heat spreader may be disposed over the exposed top surface of the bottom die and alongside the plurality of die.Type: GrantFiled: February 17, 2016Date of Patent: May 10, 2022Assignee: MICRON TECHNOLOGY, INC.Inventor: David R. Hembree
-
Patent number: 11302783Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.Type: GrantFiled: November 25, 2019Date of Patent: April 12, 2022Assignee: Infineon Technologies AGInventors: Albert Birner, Jan Ropohl
-
Patent number: 11282991Abstract: A method of producing an optoelectronic component includes providing an opto-electronic semiconductor chip including a layer sequence arranged on a substrate, wherein the layer sequence includes a contact side including two electrical contact locations, the contact side facing away from the substrate; arranging the optoelectronic semiconductor chip on an auxiliary carrier such that the contact side faces away from the auxiliary carrier; arranging a molding material above the auxiliary carrier such that a housing is formed that at least partly encloses the optoelectronic semiconductor chip, wherein the contact side is covered by the molding material; and detaching the housing from the auxiliary carrier.Type: GrantFiled: December 20, 2016Date of Patent: March 22, 2022Assignee: OSRAM OLED GmbHInventor: Siegfried Herrmann
-
Patent number: 11270931Abstract: Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the first electric path and a functional unit of the device. The isolation element separates an isolated portion in the first electric path from the second electric path, where the isolation element is configured to reduce current in the isolated portion when a signal is passing through the second electric path.Type: GrantFiled: February 9, 2018Date of Patent: March 8, 2022Assignee: Rambus Inc.Inventors: Adrian E. Ong, Dong Sik Jeong
-
Patent number: 11264527Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The integrated circuit package includes first and second active dies. Each of the first and second active dies includes a top contact disposed on the top surface of the die and a bottom contact disposed on a bottom surface of the die. The package further includes a via die having first and second vias that each extends between a top contact disposed on a top surface of the via die and a bottom contact disposed on a bottom surface of the via die, where the bottom contact of the first active die is electrically connected to the bottom contact of the first via of the via die and the bottom contact of the second active die is electrically connected to the bottom contact of the second via of the via die.Type: GrantFiled: October 1, 2018Date of Patent: March 1, 2022Assignee: Medtronic, Inc.Inventors: Mark R. Boone, Mark E. Henschel
-
Patent number: 11251396Abstract: An organic light emitting diode display is disclosed. The organic light emitting diode display includes: a substrate, an organic light emitting diode positioned on the substrate, a metal layer positioned on the substrate with the organic light emitting diode interposed therebetween, and a resin layer positioned on the metal layer and configured to reinforce a strength of the metal layer.Type: GrantFiled: August 13, 2018Date of Patent: February 15, 2022Assignee: SAMSUNG DISPLAY CO., LTD.Inventor: Kuen-Dong Ha
-
Patent number: 11244940Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.Type: GrantFiled: September 12, 2019Date of Patent: February 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Chun Chuang, Yu-Chen Hsu, Hao Chun Liu, Chita Chuang, Chen-Cheng Kuo, Chen-Shien Chen
-
Patent number: 11239233Abstract: An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.Type: GrantFiled: September 5, 2019Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Wen Wu, Hung-Jui Kuo, Ming-Che Ho
-
Patent number: 11239441Abstract: A lighting apparatus using an organic light emitting diode that has an emission area and a non-emission area, the light emitting apparatus comprises a first electrode; an organic layer disposed on the first electrode; a second electrode disposed on the organic layer; and an insulating layer disposed in the non-emission area, wherein the first electrode disposed in the emission area includes at least one metal layer and at least one dielectric layer, and wherein the first electrode disposed in the non-emission area includes at least one dielectric layer.Type: GrantFiled: July 19, 2019Date of Patent: February 1, 2022Assignee: LG DISPLAY CO., LTD.Inventors: TaeJoon Song, Jungeun Lee, Taeok Kim
-
Patent number: 11217728Abstract: A semiconductor light emitting element includes: an n-type semiconductor layer provided on a substrate; an active layer provided in a first region of the n-type semiconductor layer and made of an AlGaN-based semiconductor material; a p-type semiconductor layer provided on the active layer; a first protective layer provided on the p-type semiconductor layer and made of silicon oxide (SiO2) or silicon oxynitride (SiON); a second protective layer provided to cover a top of the first protective layer, a second region on the n-type semiconductor layer different from the first region, and a lateral surface of the active layer and made of aluminum oxide (Al2O3), aluminum oxynitride (AlON), or aluminum nitride (AlN); a p-side electrode provided contiguously on the p-type semiconductor layer; and an n-side electrode provided contiguously on the n-type semiconductor layer.Type: GrantFiled: October 30, 2019Date of Patent: January 4, 2022Assignee: NIKKISO CO., LTD.Inventors: Noritaka Niwa, Tetsuhiko Inazu
-
Patent number: 11211376Abstract: An integrated circuit includes two or more substrates stacked one over another and a first set of electrical components on one or more of the two or more substrates. The two or more substrates include a first substrate having a first predetermined doping type and a second substrate having the first predetermined doping type. The first set of electrical components is configured to form a first circuit. The integrated circuit further includes a first ground reference rail electrically connected to the first circuit, a first common ground reference rail, and a first ESD conduction element electrically connected between the first ground reference rail and the first common ground reference rail. The first ESD conduction element includes a first diode on the first substrate and a second diode on the second substrate. The first diode and the second diode are electrically connected in parallel and have opposite polarities.Type: GrantFiled: January 30, 2014Date of Patent: December 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei Yu Ma, Chia-Hui Chen, Kuo-Ji Chen