Abstract: A method is described for low temperature curing of silicone structures, including the steps of providing patterning photoresist structures on a substrate. The photoresist structures define at least one open region that can be at least partially filled with a condensation cure silicone system. Vapor phase catalyst deposition is used to accelerate the cure of the condensation cure silicone, and the photoresist structure is removed to leave free standing or layered silicone structures. Phosphor containing silicone structures that are coatable with a reflective metal or other material are enabled by the method.

Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

Abstract: A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct deposition process and patterned into one or more fins. A gate dielectric and a gate electrode are formed over the one or more fins. Alternatively, the transition metal dichalcogenide material may be formed using a deposition of a non-transition metal dichalcogenide material followed by a treatment to form a transition metal dichalcogenide material. Additionally, fins that utilized the transition metal dichalcogenide material may be formed with sidewalls that are either perpendicular to a substrate or else are sloped relative to the substrate.

Abstract: A layered metal oxide field effect material forms a heterojunction from metal oxides with different band gaps, and defines a band gap difference (?E)?1 eV. Band bending is generated at the interface of the heterojunction, such that a potential barrier is formed on the side with the larger band gap and a triangular potential well is formed on the side with the smaller band gap, and under the induction of a gate electric field, a polarized charge is generated at the interface of the heterojunction, and a large number of carriers are accumulated. Therefore, the present layered metal oxide field effect material has high carrier mobility higher than 103 cm2/V·s, and overcomes the problem that the carrier mobility of a conventional metal oxide field effect material is low, it is required to fabricate the metal oxide field effect material into a crystal phase structure with a relatively high cost, and even that a substrate thereof with a crystal phase structure is required.

Abstract: A semiconductor device includes a tube-like structure comprising a plurality of dielectric layers and conductor layers that are disposed on top of one another; a conductor tip integrally formed with a cap conductor layer that is disposed on a top surface of the tube-like structure, wherein the conductor tip extends to a central hole of the tube-like structure; and at least one photodetector formed within a bottom portion of the tube-like structure.

Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.

Abstract: A manufacturing method of TFT substrate and a TFT substrate are provided. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.

Abstract: A capacitor structure includes a substrate having thereon a storage node contact, a cylinder-shaped bottom electrode disposed on the storage node contact, a supporting structure horizontally supporting a sidewall of the cylinder-shaped bottom electrode, a capacitor dielectric layer conformally covering the cylinder-shaped bottom electrode and the supporting structure, and a top electrode covering the capacitor dielectric layer. The supporting structure has a top surface that is higher than that of the cylinder-shaped bottom electrode. The top surface of the supporting structure has a V-shaped sectional profile.

Abstract: Provided are a group III nitride semiconductor light emitting element and a method of manufacturing the same. A group III nitride semiconductor light emitting element of the present disclosure comprises in this order, in a substrate, an n-type semiconductor layer, a light emitting layer, a p-type electron blocking layer, a p-type contact layer made of AlxGa1-xN, and a p-side reflection electrode, wherein a center emission wavelength of light emitted from the light emitting layer is 270 nm or greater and 330 nm or smaller, the p-type contact layer is in contact with the p-side reflection electrode, and has a thickness of 20 nm or greater and 80 nm or smaller, and the Al composition ratio x of the p-type contact layer satisfies the following Formula: 2.09?0.006×?p?x?2.25?0.006×?p where ?p is the center emission wavelength in nanometer.

Abstract: The array of gallium-nitride (GaN) nanocolumns have quantum wells in a polar c-plane or in a semi-polar plane to emit light directed to ends of the nanocolumns and an interstitial filler material with light emitted in the nanocolumns being guided to exit from an end of the nanocolumns.

Abstract: An integrated circuit is provided with a memory cell array comprising poly lines, semiconductor lines extending in a first direction and transistor devices, wherein gates of the transistor device are formed in portions of the poly lines and channels of the transistor devices are formed in the semiconductor lines and wherein at least one portion of at least one of the poly lines runs across at least one of the semiconductor lines in a second direction inclined to a direction perpendicular to the first direction at an inclination angle of more than, for example, 5° or 10°, as measured from the direction perpendicular to first direction.

Abstract: A method of manufacturing a light emitting device is provided. The method includes providing a lead frame including a plurality of light emitting devices each including: a light emitting element; a resin molded body including a lead electrode on which the light emitting element is mounted, and a light-shielding member which supports the lead electrode and has a recess accommodating the light emitting element; and a light-transmissive member disposed in the recess. The method further includes: providing a mask including a plurality of through holes, and overlaying the mask on the lead frame so that the resin molded body and the light-transmissive member are exposed at the through holes; and perforating abrasive blasting by blowing a particulate material on a surface of the resin molded body and a surface of the light-transmissive member.

Abstract: A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.

Abstract: A light emitting element includes a semiconductor layer which is in a planar shape of a polygon at least of a pentagon, a second electrode provided on the semiconductor layer, and a first electrode provided on the semiconductor layer and having a first pad portion, a first extension portion that extends from the first pad portion along an imaginary circle to which the first pad portion is tangent on the inside and whose center is at the same location as center of gravity of the polygon shape, and a second extension portion that extends along the imaginary circle from the first pad portion on the opposite side from the first extension portion.

Abstract: There is provided a method of forming a layer, comprising depositing a seed layer on the substrate and depositing a bulk layer on the seed layer. Depositing the seed layer comprises supplying a first precursor comprising metal and halogen atoms to the substrate; and supplying a first reactant to the substrate. Depositing the bulk layer comprises supplying a second precursor comprising metal and halogen atoms to the seed layer and supplying a second reactant to the seed layer.

Abstract: A micro panchromatic QLED array device based on a quantum dot transfer process of deep silicon etching templates. Array-type square table structures pass through a p-type GaN layer and a quantum well active layer and are deep to an n-type GaN layer are disposed on a blue LED epitaxial wafer, wherein micro holes are formed through etching in the structures. Every 2*2 table structures constitute an RGB pixel unit. Among the four micro holes, three of the holes are filled with red light, green light and yellow light quantum dots respectively, and one of the holes emits blue light/is filled with a blue light quantum dot. Micro holes in a silicon wafer are formed through etching with a deep silicon etching technology; the micro holes in the silicon wafer are aligned with quantum dot filling areas on a micro-LED.

Abstract: A lighting device includes a substrate having a light emitting area and a non-light emitting area surrounding the light emitting area, a light emitting part in the light emitting area, a first inorganic layer on the light emitting part and the non-light emitting area, a first organic layer on the first inorganic layer overlapping the light emitting part, a second inorganic layer on the first organic layer, a protruding part on the first inorganic layer of the non-light emitting area, and a cover layer on the protruding part.

Abstract: A display apparatus includes thin-film transistors respectively provided for pixels arranged in a matrix form, one or more driving circuits provided at a side of one end of the display panel, a plurality of signal lines to each connect more than one of the plurality of thin-film transistors arranged in one line in the matrix form to the driving circuit, a plurality of spare lines formed to be connectable to any of the plurality of signal lines in an outer area of a display panel, and arranged separated from one another in an opposing region in the outer area, the opposing region being opposed to the driving circuits across the display area, and a metal pattern overlapping a first spare line and a second spare line with an insulating layer therebetween, so as to be connectable to the first spare line arranged in a first region and the second spare line arranged in a second region.

Abstract: A method includes forming a dielectric layer over a conductive feature, forming an opening in the dielectric layer, and plating a metallic material to form a redistribution line electrically coupled to the conductive feature. The redistribution line includes a via in the opening, and a metal trace. The metal trace includes a first portion directly over the via, and a second portion misaligned with the via. A first top surface of the first portion is substantially coplanar with a second top surface of the second portion of the metal trace.

Abstract: Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.