Abstract: A serializer and a deserializer are disclosed and shown operating singly or as a pair. The invention operates independently from any outside system reference clock. The inventive system provides an internal bit clock that serializes the data when sending and de-serializes the data when receiving. A bit clock or pulse travels with the data word bits to define when a bit is stable. The system uses word boundary bits operating with a bit clock to distinguish different data words, as described in the parent application. The system operates either synchronously or asynchronously with the base computer or other such digital system, including I/O devices. The invention finds use where new data to be sent is strobed into the serializer, but also where a change in the data bit content itself will cause the changed data to be loaded into the serializer and sent bit by bit. The system operates where new data is strobed or loaded by the serializer (not the base computer system) when the last data word has been sent.

Abstract: A converter 10 selects desired unit current cells from unit current cells 16, 18, 20, 22 in accordance with an input code 102, and supplies currents from the selected cells to a load resistor 24 to generate an analog voltage Vdac. By supplying the constant current comprised of the currents from the selected cells and currents from non-selected cells to an offset adjuster circuit 26 including an adjusting resister 28 to generate an offset voltage Vos, the converter 10 can output a voltage Vout which is the sum of the analog voltage Vdac and the offset voltage Vos.

Abstract: A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).

Abstract: A transmitter for a data communication system that comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular signaling cell, and integrating for a second interval with a negative polarity within the particular signaling cell, to produce output representing the codewords. A sense circuit produces an output data stream.

Abstract: A first amplifier circuit samples and amplifies an input analog signal by a gain of 0.8 and outputs the amplified signal to a first subtracter circuit. A first analog-digital converter circuit converts the input analog signal into a digital value so as to retrieve the higher 4 bits. A first digital-analog converter circuit converts the digital value produced by conversion by the first analog-digital converter circuit into an analog value. The first subtracter circuit subtracts an output analog signal from the first digital-analog converter circuit from an output analog signal from the first amplifier circuit. The output analog signal from the first digital-analog converter circuit is amplified by a gain of 0.8. By setting the gain of the first amplifier circuit to be below 1, an input voltage range is extended.

Abstract: The present invention discloses a method and related apparatus for compensating a gain mismatch between a first DAC and a second DAC. The second DAC is connected to a gain amplifier. The method includes the following steps. Determine a first gain value corresponding to the first DAC. Control the gain amplifier with a first control value and determine a second gain value corresponding to the second DAC and the gain amplifier. Control the gain amplifier with a second control value and determine a third gain value corresponding to the second DAC and the gain amplifier. Without utilizing a predetermined characteristic parameters, determine a calibration control value according to the first, second, third gain values, and the first and second control values. Control the gain amplifier with the calibration control value to compensate for the gain mismatch between the first DAC and the second DAC.

Abstract: An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.

Abstract: An apparatus comprising a first quantizer circuit, a memory and a second quantizer circuit. The first quantizer circuit may be configured to generate a first intermediate signal in response to (i) an input signal and (ii) a first scaling signal. The memory may be configured to (i) store the first intermediate signal and (ii) present a second intermediate signal, in response to an address signal. The second quantizer circuit may be configured to generate an output signal in response to (i) the second intermediate signal and (ii) a second scaling signal. The second quantizer circuit has a bit-width greater than the bit-width of the first quantizer circuit.

Abstract: Trimming by disconnecting a fuse connected in parallel to a feedback resistor of an amplifier circuit would cause a variation in voltage value due to a remaining resistance component. A voltage generator circuit is provided therein with a D/A converter circuit of an R-2R ladder resistor network type circuit. The D/A converter circuit is provided with a first switch circuit to an eighth switch circuit, corresponding to each bit, which are switched to set a digital value. Each switch circuit, which is provided with a fuse for providing a fixed voltage value, allows the fuse to be disconnected to fix the voltage value to a value obtained by inverting the initial value. The setting circuit controls the switching operation of each switch circuit, thereby simulating an electrical state of a fuse being disconnected before the fuse is actually disconnected.

Abstract: A method and apparatus for sampling an analog input signal and storing digital values in a memory, wherein a sequence of clock pulses is generated at a predetermined frequency and a pseudo-random integer is generated at every sampling pulse. The sequence of clock pulses is divided by the integer to select one last pulse from every series of clock pulses. A sequence of sampling pulses is formed by generating a second pseudo-random integer and delaying the selected clock pulse. An analog input signal at the delayed clock pulse is sampled and converted to a predetermined digital format. The current signal sample value is stored in a memory.

Abstract: Improved methods for the calibration, in particular for self-calibration, of an A/D or D/A converter with weighted network (CN) are proposed. Only a relevant part of the weights (C0, C1, C2, Cn) is calibrated by measurement. In addition, by iterative repetition of measurements used for the calibration a noise is used for increasing a resolution. Finally, possibilities for dealing with the offset are illustrated. Complementary equations are set up and the offset is eliminated by subtraction. If an equation necessary for calibration cannot be directly set up because of an overflow, this is resolved by using special binary codes which indicate which weights are enabled and/or disenabled, and their conversion.

Abstract: A current source cell includes a current source providing a first current where the first current can be calibrated, first and second switches coupled to steer the first current to respective first and second output terminals in response to respective first and second control signals, and a latch circuit generating the first and second control signals. The latch circuit drives the first and second control signals to a first logical state to cause the first and second switches to open. The first current is then calibrated. After calibration, the latch circuit drives the first and second control signals to have logical states that correspond to a data signal as triggered by a clock signal where the first and second control signals have inverse logical states. One of the first and second switches is closed to steer the first current to a respective one of the first and second output terminals.

Abstract: A power amplifier circuit includes an adjustable gain power amplifier for amplifying an RF input signal. An isolated node in the adjustable gain power amplifier is isolated from the output load by a gain stage of the adjustable gain power amplifier. The power level of a signal at the isolated node corresponds to the power level of a signal at the output load. A detector is either capacitively coupled to the isolated node or connected by a direct current (DC) connection. The detector detects the power level of the signal at the isolated node. The detector generates a power level indicator that is sent to a gain control circuit. The gain control circuit adjusts the gain of the adjustable gain power amplifier to maintain a constant drive level at the isolated node.

Abstract: A first and second signal source are coupled to an analog output in a digital input signal dependent configuration. The signal sources so that a contribution of their source signals adds up in a first or a second direction when the digital input assumes a first or a second value respectively. The source signals counteract each other when the digital input signal assumes a third value. The signs with which the source signals contribute to the analog signal level for the third value are alternated, so that both signs occur substantially equally frequently for each of the signal sources. The spectral density of a deviation signal due to said alternating is concentrated at high frequencies. In an embodiment the spectral density is moved to high frequency by modulating the alternation onto a high frequency alternation that is used to generate return to zero levels between digital input signal dependent levels.

Abstract: A digital to analog converter includes a digital processor having an input port adapted to receive an input signal and an output port coupled to an input port of an analog filter wherein the digital processor includes a digital feedback loop which compares a reference digital voltage with a digital voltage provided by a digital model of the analog filter. Using a completely digital feedback loop which compares an input digital voltage with the digital voltage from the digital model of the analog filter results in a single bit digital to analog converter having improved accuracy for a given clock rate and filter. The next digital state of the converter (i.e. ‘0’ or ‘1’) is selected based upon a comparison of the input (or reference) voltage with the digital voltage provided by the digital feedback loop. The digital converter output is then fed to the analog filter. If the analog filter matches the digital model, then the analog voltage will match the digital voltage, and therefore the reference voltage.

Abstract: Disclosed is a digital sampling rate converter for compensating for a drop of an in-band signal, the digital sampling rate converter including a CIC (Cascaded Integrator-Comb) decimator for performing a decimation operation at a first decimation ratio based on an overall decimation ratio, for an input signal; a sub-decimator for performing a decimation operation at a second decimation ratio for a signal output from the CIC decimator; and a compensation unit for performing at least two multiplication operations and two addition operations with respect to a signal output from the sub-decimator using a lowest operation clock frequency in an assigned band.

Abstract: The invention relates to a digital-to-analog converter for converting a digital value into an analog quantity, said converter comprising current sources switched as a function of said digital value in order to generate an output current reflecting the value of said analog quantity. The converter comprises means of generating a correction current added to said output current, said correction current comprising a component proportional to the square of said output current. Use: Digital-to-analog converter.

Abstract: A training method of a digital-analog converter is provided. The digital-analog converter comprises a plurality of parallel capacitors, each of which is floatingly coupled to a plurality of correcting capacitors. Two voltages outputted from the digital-analog converter are received and compared. When a latter output voltage is lower than or equal to a former output voltage, the correcting capacitor is used to correct the capacitor corresponding to the latter output voltage until the latter output voltage is higher than the former output voltage. When the latter output voltage is higher than the former output voltage, a new voltage is outputted from the digital-analog convert and compared with the latter output voltage. The steps of comparing and correcting are repeated until every latter output voltage is higher than every former output voltage.

Abstract: Techniques are provided for applying modulation constraints to data by using periodically changing symbol mappings to replace certain prohibited error prone data patterns. Initially, user data in a first base is mapped to integers of a second base using a base conversion technique. The integers in the second base correspond to symbols. Subsequently, periodically changing symbol mappings are performed during which prohibited symbols generated during base conversion are mapped to permitted symbols. The periodically changing symbol mappings occur in multiple phases, and the prohibited symbols are different in each phase. The resulting data is processed by a precoder in some embodiments.

Abstract: In the coding device and method, m-bit information words are converted into n-bit code words such that the coding rate m/n is greater than 2/3. The n-bit code words are divided into a first type and a second type, and into coding states of a first kind and a second kind such that an m-bit information word is converted into an n-bit code word of the first or second kind if the previous m-bit information word was converted into an n-bit code word of the first type and is converted into an n-bit code word of the first kind if the previous m-bit information word was converted into an n-bit code word of the second type. In one embodiment, n-bit code words of the first type end in zero, n-bit code words of the second type end in one, n-bit code words of the first kind start with zero, and n-bit code words of the second kind start with zero or one.