Abstract: The invention CONCERNS a device for reconfiguring an assembly of N basic electronic modules associated with k redundant modules comprising: N multiplexers each having a first terminal (di) capable of being connected to k+1 second terminals connected to the k+1 input/output terminals of a sequenced group of modules consisting of a basic module (Ui) and k other modules; N+k triggers (Fi) indicating a good or faulty condition of one of the N+k modules; and logic means associated with each multiplexer of rank j, where j is an integer ranging between 0 and N, to determine the number of triggers of rank 0 to j indicating a faulty condition, to determine the number of modules of the sequenced group associated with the module of rank j, to be counted to find a number of good modules equal to the first number, and to convert the first terminal of the multiplexer to its second terminal of rank equal to the second number.

Abstract: A system and method for reducing reflections in a transmission line and for recovering energy from the load in the transmission during the process. At least three drive signal levels are utilized. The transition from the second level to the third level during a rising transition and the transition from the second level to the first level during a falling transition is timed to coincide with the arrival of the reflected signal from the immediately-preceding transition. A capacitor is advantageously used as the source for the intermediate drive signal levels and advantageously facilitates energy recovery and conservation.

Abstract: The values X(n) input to a current-steering digital-to-analog converter (49) are modified (41) before the actual conversion to compensate for conversion errors of the digital-to-analog converter. The input values are modified according to a model (43) of the digital-to-analog converter in which each output value of the digital-to-analog converter Y(n) is a sum of a desired value directly proportional to the respective input value and an error. The error is a product of the settled output value, i.e. the difference between the desired value and the previous output value Y(n?1) actually provided by the digital-to-analog converter, and a relative step error that is a function only of the respective input signal and is stored in a table. The relative step error can be a function also of the previous output signal and of the previous input signal. This model has a low complexity and is suitable for on-chip implementation.

Abstract: A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin?) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.

Abstract: A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has drivers that generate drive signals based on received digital input signals. The drive signals are received at switches in the analog section of the DAC. The switches generate analog signals therefrom. Swing values of the drive signals are limited to a predetermined amount to substantially eliminate glitch in the analog signals. The drivers can be coupled between first and second nodes that receive different power signal values. Controlling the power signal values allows for the limiting of the swing values. Limiting the swing values limits stored charged in the first and second switches, which substantially eliminates glitch in the analog signals. This can be done regardless on environmental variances (e.g., temperature variance) during operation of the DAC.

Abstract: An linear optical sensor charged-coupled topology using single-stage inverting charge-coupled amplifier driving an analog-to-digital converter which uses the converter full-scale reference as a precharge level. Since an offset in the range of 100–200 mV is introduced in the charge amplifier, a corresponding offset is also introduced into the ADC to allow the amplifier to more quickly drive the amplifier output to a low level. The converter offset is proportional to the converter reference to ensure that it is controlled and tracks the reference.

Abstract: In one embodiment of the present invention, an amplifier circuit is provided which includes a predistorter coupled to a power amplifier. An error detector is coupled to the signal input of the predistorter via a delay circuit and to the power amplifier output. The error detector output is coupled to a delta-sigma modulator and the output of the delta-sigma is coupled to the control input of the predistorter. The predistorter may be constructed to provide an output selected from a set of output characteristic curves, in response to a control signal at the control input. The control input of the predistorter may be a multi-bit discrete input, which may be a binary input, such as for example, a three bit binary input.

Abstract: The objective is to provide a sampling/holding circuit that can operate at high speed and low power consumption. The sampling/holding circuit has multiple sampling units 2-1˜k. Each sampling unit has input terminals 1-1˜k and output terminals 3-1˜k. The values received at the input terminals are sampled, and the sample values are accumulated. Also, the accumulated sample values are generated at output terminals 3-1˜k. One holding unit 6 has an input terminal 5 and an output terminal 7, which are shared by the multiple sampling units. By multiplexing the outputs of the multiple sampling units, multiplexing unit 4 connects any output to the input of holding unit 6. Holding unit 6 holds the sample value and generates it at output 7.

Abstract: A data shuffler apparatus shuffles input bits to perform dynamic element matching. The shuffler apparatus includes N input shufflers, each input shuffler having N input terminals and N output terminals, each input terminal of each input shuffler receiving a respective one of the input bits. The apparatus also includes N output shufflers, each output shuffler having N input terminals and N output terminals, the input and output shufflers being interconnected such that each of the N output terminals of each input shuffler is connected to a respective input terminal of a different one of the N output shufflers.

Abstract: Methods and systems are provided for synchronizing various time-stamped data streams. The data streams can be synchronized to another data stream or to a point of reference such as a reference clock. In one embodiment, synchronization processing takes place in association with a filter graph comprising multiple filters. The filter graph is configured to process multiple timestamped data streams for rendering the data streams in accordance with data stream timestamps. A synchronization module is provided and is associated with the filter graph queries individual filters of the filter graph to ascertain input timestamp-to-output timestamp mappings. The module computes adjustments that are to be made to output timestamps in order to synchronize the data streams, and then instructs queried filters to adjust their output timestamps in accordance with its adjustment computations.

Abstract: An analog signal outputting circuit comprises two unit analog circuits for outputting an analog signal, corresponding to levels “?1” or “1”, and a low-pass filter for smoothing the analog signal output from the two unit analog circuits, as selected by codes output from the four-valued delta-sigma modulator. In case the input signal is ?2 or +2, outputs of the unit analog circuits are summed together to output an analog signal corresponding to ?2 or +2. In case the input signal is ?1 or +1, outputs of the unit analog circuits are alternately used to output an analog signal corresponding to ?1 or +1 to reduce the non-linearity error resulting from variations in the analog devices.

Abstract: A semiconductor integrated circuit comprises a digital-to-analogue converter for converting a digital signal into an analogue signal to output an analogue current signal, a current-to-voltage converter for converting the analogue current signal output by the digital-to-analogue converter, into an analogue voltage signal whose level has been controlled, and a filter for filtering the analogue voltage signal converted by the current-to-voltage converter. The current-to-voltage converter converts the current signal into the voltage signal in which a factor variable in accordance with manufacturing process conditions and/or environmental conditions has been corrected.

Abstract: A method for decoding an input bitstream is disclosed. The method generally includes the steps of (A) generating an intermediate bitstream having an intermediate encoded format by converting the input bitstream having an input encoded format and an input order, (B) storing the intermediate bitstream in the input order and (C) generating an output signal having an output order by decoding the intermediate bitstream.

Abstract: Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages using thermometer coding. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs, wherein the capacitors are switched according to a thermometer code to reduce differential converter non-linearity.

Abstract: An analog unit system according to this invention comprises a first analog unit having first storage means for storing a first factory setting value and a first user setting value, second storage means for reading the first factory setting value and the first user setting value out of the first storage means and storing the setting values, operation means for calculating a second user setting value based on the first factory setting value and the first user setting value read out of the second storage means, and a second analog unit having third storage means for storing the second user setting value calculated by this operation means and thereby, adjustment and calibration of the user setting value can automatically be performed by simple manipulation with respect to the analog unit in which the user setting value is not set.

Abstract: A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (“DAC”) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N.

Abstract: An A/D converter converts a sine and cosine wave output of a resolver to form a digital sine and cosine. A microcomputer uses an absolute value of digital sin ? as an address to retrieve ? from a memory containing angle values between 0° and 90°, if the absolute value of sin ? is between 0 and 0.707. Otherwise, if the absolute value of sin ? is between 0.707 and 1, cos ? is used as an address to retrieve ?. The polarities of sin ? and cos ? are used to determine a quadrant and an associated offset including 0°, 180°??, 180°+?, and 360°??, which is combined with ? such that the final angle of the rotor axis is obtained.

Abstract: An Nth-order sigma-delta analog-to-digital converter (ADC) system having multilevel quantized feedback. A multilevel quantized feedback stage incorporates a multibit, current-mode digital-to-analog converter (DAC). In one embodiment, reference current sources for the DAC may comprise a plurality of floating-gate MOS transistors so that analog nonvolatile precision linearity trimming of the feedback DAC may be accomplished. Calibration of the DAC may be performed at a relatively low refresh rate, for example, only at instances when the sigma-delta ADC system is activated.

Abstract: A demodulating circuit includes a differentiating circuit that outputs a differentiated signal indicating voltage changes at rising and falling edges of a received pulse signal, and a hysteresis comparator that compares the differentiated signal with upper and lower threshold voltages, thereby generating a demodulated logic-level signal. The differentiating circuit can rapidly track variations in the direct-current offset of the received pulse signal. Positive feedback can enable the hysteresis comparator to maintain the correct output logic level during runs of 0's or 1's of arbitrary length in the received pulse signal. The demodulating circuit consumes comparatively little power, and is particularly useful for receiving signals transmitted in bursts.

Abstract: A method for correcting A/D converted output data which corrects digital data obtained by A/D conversion of an analog signal, comprising forming an at least first order polynomial curve approximating an input/output characteristic curve of A/D conversion in a range of input of the analog signal, setting an ideal input/output characteristic line of A/D conversion, deriving a conversion equation for converting coordinates of a point on the approximation polynomial curve to a point of the ideal input/output characteristic line for the same analog signal value, and using this conversion equation to convert A/D converted digital data so as to correct non-linearity of the output data.