Abstract: A transmit signal generated by the baseband processor in a translational loop type RF transmitter is “pre-distorted” so as to counter act magnitude distortion and group delay variation imposed by a narrow PLL signal filter. The pre-distortion occurs in two steps: a magnitude equalizer in the baseband processor pre-distorts the amplitude of the transmit signal according to the inverse of the PLL signal filter magnitude response, and a group delay equalizer linearizes the phase response of the entire transmitter chain, i.e., pre-distorts the transmit signal such that the combined phase response of magnitude equalizer, group delay equalizer, and PLL signal filter is linear. With such pre-distortion, a loop filter is provided for with component values that define a relatively small bandwidth for the loop filter to filter spurious tones that result from an IF reference feedthrough to a voltage controlled oscillator of the translational loop.

Abstract: A voltage-to-time conversion circuit compares a ramp-wave voltage, which steps up at a certain gradient, with each of a reference voltage, an input voltage, and a reference voltage, and produces a PB pulsating signal representing the times which the voltages require for having a predetermined relationship to the ramp-wave voltage. An encoder circuit converts the times into coded data items according to the ratios of the times to a common unit time. A normalization circuit determines a conversion characteristic curve on the basis of the coded data items, into which the times required by the reference voltages are converted, and A/D-converted values predefined for the reference voltages, and fits the coded data, into which the time required by the input voltage is converted, to the characteristic curve. Thus, the A/D-converted value of the input voltage Vin is calculated.

Abstract: An analog-to-digital converting apparatus for rapidly processing a plurality of analog input signals at a high rate and a display device using the same. The apparatus includes a clock signal generator that generates a clock signal with a predetermined frequency; a control signal generator that generates a switching control signal using the clock signal; a multiplexer (MUX) that receives and selectively outputs signals of the plurality of analog input signals according to the switching control signal; and an analog-to-digital converter (ADC) that converts an analog signal selected and output by the MUX to a digital signal.

Abstract: Skew-tolerant Gray codes have the property that consecutive code words differ in only one co-ordinate position, and the additional property that, in each consecutive group of three consecutive code words, the first and third code words differ in only two adjacent coordinate positions.

Abstract: Procedures for decorrelating the branch signals of a signal adjuster of an amplifier linearizer are presented herein. The decorrelation procedures can be performed with or without self-calibration.

Abstract: A method and apparatus for an amplifier, such as a radio frequency amplifier embodied as an integrated circuit is disclosed. Embodiments provide for a wide range of operating powers with good energy efficiency at many power levels. Resonant components act to provide consistent operating parameters over the wide range of power levels used. The invention may operate in the microwave region or at other RFs.

Abstract: A current steering folding circuit is provided. The current steering folding circuit includes a load and at least one current source for drawing a current from the load. The current steering folding circuit also includes a first output signal terminal for providing a first output signal, and a second output signal terminal for providing a second output signal. A current steering section is also provided. The current steering section steers the current between the first output signal terminal and the second output signal terminal based on an input signal. The first output signal is substantially equal to the second output signal for N values of the input signal. Advantageously, the number of current sources does not exceed N.

Abstract: Devices for performing analog-to-digital conversion with reduced noise. In one implementation, an analog-to-digital converter includes at least one internal digital-to-analog converter (DAC) that comprises a plurality of analog components and converts an intermediate digital signal into an associated intermediate analog signal, a dynamic element matching (DEM) circuit coupled to the DAC to permute configurations of the analog components within the DAC, a noise cancellation circuit and a digital subtractor block. The noise cancellation circuit is coupled to receive a first digital sequence comprising a component of a digitized representation of an analog output of the DAC, and a second digital sequence representing a state of the DEM circuitry. The noise cancellation circuit is operable to combine the first and the second digital sequences so as to estimate a digital representation of a DAC noise caused by error sequence introduced mismatches among the analog components within the DAC.

Abstract: An aspect of the present invention simplifies the implementation of complex clock designs in field programmable devices (FPD). To implement a circuit logic containing base sequential elements (e.g., D flip-flops) with corresponding circuit clocks, a number of modified sequential elements equaling the number of base sequential elements may be employed. Each modified sequential element (contained in FPD) receives a global clock, corresponding circuit clock and a data value. A base sequential element (contained in modified sequential element) transitions to a next state only after occurrence of a transition on a corresponding circuit clock and the transition to said next state may be timed according to the global clock. By timing the transitions according to the global clock, several undesired results may be avoided.

Abstract: A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of integrated circuit chip area, without requiring analog calibration circuits. The DAC calibration system includes a main DAC to be calibrated, a memory, and calibration logic circuitry for performing arithmetical operations. The memory stores a predetermined number of digital code values in respective memory locations, which are indexed by corresponding voltage values. The digital code values represent DAC input code values which, when applied to the main DAC, would generate the corresponding index voltage values as DAC output voltage levels. The stored DAC input code values and the corresponding DAC output voltage levels, which are determined using an external tester, define piecewise linear (PWL) breakpoint code values of a PWL approximation of the DAC transfer function.

Abstract: A D/A converter in which reference voltage around which voltages outputted vary is not generated by an amplifier in order to reduce electric current consumption. A resistor circuit divides power supply voltage and outputs a plurality of voltages which make up an arithmetic progression. A decoder circuit decodes a digital signal and outputs a control signal. A switching circuit is turned on/off in accordance with the control signal sent from the decoder circuit and selects and outputs one of the plurality of voltages outputted from the resistor circuit.

Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output.

Abstract: Presented herein is a system, method, and apparatus for decoding variable length codes. In one embodiment, there is presented a method for decoding variable length coded symbols. The method comprises storing one or more symbols from a plurality of variable length coded symbols in a first register; storing a portion of a particular symbol from the plurality of variable length coded symbols in the first register; storing another portion of the particular symbol in a second register; and storing the contents of the first register in memory after storing the portion of the particular symbol in the first register.

Abstract: Signal converters are provided that accurately process dc-coupled source signals in the presence of different predetermined voltage and current source requirements. Processing structures are described that satisfy these requirements while providing accurate control of common mode levels along a processing path and accurate reduction of converter offset errors.

Abstract: A latch architecture for driving unit current cell of a current-steering digital-to-analog converter (DAC) which reduces the drain-source voltage variation of the output current-source transistors and reduces the coupling of unwanted injection of input digital signals as well as clock signals is presented herein. Moreover, this latch helps to achieve lower glitch during code transition with improved dynamic performance. The latch effectively uses the intrinsic RC delay of most transistors within the latch architecture in order to achieve optimal crossing points of complementary control signals. Unwanted input injection or cross-talk is reduced by introducing transistors (904, 906, 932 and 934) that are off during code transitions without compromising the DAC update speed. Conflicts between currently held and new inputs are avoided in an effort to reduce the harmonic distortion.

Abstract: A semi-conductor circuit arrangement for a continuous time sigma delta modulator for adding analog input signals to a digital fed back signal and for quantizing the totalled signal comprises a voltage to current conversion circuit (10), an adding circuit (20) with a resistor ladder, a quantizing circuit (40) with comparator elements (45) and a digital to analog conversion circuit (30). For each comparator element (45) its respective input signal is formed by a voltage which is released between a tap in front of a corresponding tapping resistor (22) in a first string of the resistor ladder and a tap in front of a corresponding tapping resistor (22) in a second string of the resistor ladder.

Abstract: The present invention provides a dielectric resonator, a dielectric filter, a dielectric duplexer capable of reducing leakage of electromagnetic waves and capable of being miniaturized, and a communication apparatus incorporating the same. In each of the dielectric resonator and filter, inside a dielectric block, there is formed a L-shaped inner-conductor-formed hole having a bend at some point of the hole in a manner extending from an outer surface of the dielectric block to a surface perpendicular to the outer surface. An inner conductor is formed on the inner surface of the inner-conductor-formed hole. On the substantially entire outer surfaces of the dielectric block, there is disposed an outer conductor, with one end of the inner-conductor-formed hole open-circuited and the remaining end of the hole short-circuited. Around the edge of the open-circuited end there is formed an outer coupling electrode.

Abstract: A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has a driver portion that generates drive signals based on received respective digital input signals. The drive signals are received at respective switches in the analog section. The driver portion includes logic gates that are used to generate the drive signals, such that a rise and fall time of complementary pairs of drive signals are substantially equal. The driver portion can optionally include an acceleration system to accelerate the rise and fall times of the drive signals. The switches generate respective analog signals from the drive signals.

Abstract: Embodiments of a method of generating Huffman code length information are disclosed. In one such embodiment, a data structure is employed, although, of course, the invention is not limited in scope to the particular embodiments disclosed.

Abstract: Method and circuit for stabilizing the output power of a power amplifier, operated with signals having a large peak-to-average ratio and fed by a DC power supply with fluctuating output voltage. An allowable fluctuating range for the voltage output from the DC power supply and a constant voltage level are determined. A controllable voltage enhancement circuitry that can output an enhancement voltage is provided. The input of the voltage enhancement circuitry and a first DC supply path are connected to the output of the DC power supply. The output of the voltage enhancement circuitry is connected to a second DC supply path. While the instantaneous value of the fluctuating output voltage is lower than the constant voltage level, the voltage enhancement circuitry generates an enhancement voltage that causes the sum of the voltages supplied through the first and the second supply paths, to be identical to the constant voltage level.