Abstract: A voltage setting circuit includes a voltage setting region setting a voltage level corresponding to a maximum value in amplitude of a signal output from an OTA circuit, a voltage setting region setting a voltage level corresponding to a minimum value in amplitude of the signal, and an intermediate voltage setting region setting a voltage intermediate between the voltages set by the above two regions. This intermediate voltage is input to a common mode feedback circuit and in accordance with the intermediate voltage the common mode feedback circuit generates a common mode voltage fed back to the OTA circuit.

Abstract: DC offset is compensated for in an analog front end (AFE) circuit having an amplifier and an analog-to-digital converter (ADC). First data processed by the ADC are low pass filtered and estimated DC offset data of the ADC are obtained in ADC DC offset calibration mode. Second data processed by the ADC and the amplifier are low pass filtered, and a first DC offset of the ADC are substantially removed from the filtered second data by subtracting the estimated DC offset data from the filtered second data, thereby obtaining second compensated DC offset data of the amplifier in an amplifier DC offset calibration mode. The second compensated DC offset data is iteratively improved and first compensated DC offset data of the amplifier are obtained. The first compensated DC offset data are transformed into an analog signal, and the analog signal is subtracted from an input signal of the amplifier during operation mode.

Abstract: An error correction circuit and a folding ADC are provided. In the folding ADC, the range of the input voltage to an upper ADC circuit and to a lower ADC circuit is shifted by a predetermined voltage toward higher and lower electric potential sides. The error correction circuit outputs the conversion result of the upper bits as is, or corrects the conversion result of the upper bits by either subtracting or adding 1 from or to the conversion result of the upper bits in accordance with the least significant bit within the conversion result of the upper bits and in accordance with the polarity of a code having different polarities between a period in which the voltage level of one folding signal among a plurality of folding signals output from the folding circuit is higher than the center level and a period in which the voltage level is lower.

Abstract: A scalable encoder having a first encoder, a decoder and a second encoder includes, above that, a phase distorter to reduce a non-linear frequency-dependent phase distortion introduced by the first encoder or by the decoder, which results in an increased difference signal of a comparator. Thus, a difference signal with less energy is obtained that the second encoder can encode with less bits, that is with a higher bit efficiency.

Abstract: An AD converter capable of achieving both an improved processing speed and a reduced circuit area in good balance. The AD converter pipelines analog-to-digital conversion by using a two-stage configuration consisting of a first conversion unit, or the prior stage, and a second conversion unit, or the subsequent stage. The first conversion unit is a conversion unit of noncyclic type. The second conversion unit is a conversion unit of cyclic type. The second conversion unit is given a conversion processing speed higher than that of the first conversion unit so that the second conversion unit performs cyclic processing twice while the first conversion unit performs conversion processing once.

Abstract: A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.

Abstract: A voltage detection circuit. A second NMOS transistor has a gate coupled to the gate of a first NMOS transistor. A comparator has input terminals, and an output terminal. A first resistor is coupled between the first input terminal and the source of the first NMOS transistor, a second resistor is coupled to the comparator and the first resistor, a third resistor is coupled between the second resistor and the comparator, and a fourth resistor is coupled between the second and third resistors, and ground. A first PMOS transistor has a gate coupled to the gates of the first and second NMOS transistors. A second PMOS transistor has a connected gate and drain, a source coupled to the gates of first and second NMOS transistors, a drain coupled to ground, and an n-well directly connected to the gates of the first and second NMOS transistors.

Abstract: The present invention is provided with a first, a second and a third differential amplifier which operate at a source voltage with respect to a reference voltage or a voltage between these; an output stage having a first and a second transistor driven complimentarily; a first resistor connected to an input terminal; a second resistor connected to an output of the first differential amplifier circuit; and a first and a second feed back resistor connected to an output terminal of the output stage circuit.

Abstract: Digital to analog converters (DAC). A first MSB DAC receives MSB data of a first digital video signal in a first clock period, and outputs a first voltage range signal. A second MSB DAC receives MSB data of a second digital video signal in a second clock period, and outputs a second voltage range signal. A delay circuit receives LSB data of the first digital video signal in the first clock period, and outputs the signal in the second clock period. A LSB DAC outputs first image data according to the first voltage range signal and the LSB data of the first digital video signal in the second clock period. A first switch is connected between the first MSB DAC and the LSB DAC, and is turned on to provide the first voltage range signal to the LSB DAC in the second clock period.

Abstract: In the coding device and method, m-bit information words are converted into n-bit code words such that the coding rate m/n is greater than 2/3. The n-bit code words are divided into a first type and a second type, and into coding states of a first kind and a second kind such that an m-bit information word is converted into an n-bit code word of the first or second kind if the previous m-bit information word was converted into an n-bit code word of the first type and is converted into an n-bit code word of the first kind if the previous m-bit information word was converted into an n-bit code word of the second type. In one embodiment, n-bit code words of the first type end in zero, n-bit code words of the second type end in one, n-bit code words of the first kind start with zero, and n-bit code words of the second kind start with zero or one.

Abstract: A system and method for analog-to-digital conversion using digital pulse width modulation (PWM) is disclosed. The method and system according to the disclosed invention converts an analog input signal to a digital signal in pulse code modulated (PCM) form. The disclosed invention uses a feedback circuit to perform PWM of the analog input signal. The PWM signal is then decimated to obtain the digital signal in PCM form. The system according to the disclosed invention requires lower operating frequency and dissipates lesser power than prior art systems providing the same sampling frequency and resolution. The operation at a lower frequency is achieved by obtaining two samples from every pulse of the PWM signal; the first sample being obtained from the right duty ratio, and the second sample being obtained form the left duty ratio. Further, the disclosed invention has lesser implementation complexity and higher signal-to-noise ratio than prior art.

Abstract: An improved circuit for a delta-sigma digital-to-analog converter comprises integrating operational amplifier, sampling capacitors, integrating capacitor, and a voltage divider consisting of a plurality of sampling capacitors. Three trigger signals of different phases are designed to control three sets of switches, a first trigger signal only turns on and off a first set of switches, so as to charge the plurality of sampling capacitors, a second trigger signal only turns on and off a second set of switches, so as to enable the charge on one of the sampling capacitor and the charge on the integrating capacitor to be averaged, a third trigger signal only turns on and off a third set of switches, to enable the plurality of sampling capacitors to be discharged.

Abstract: A system and method to improve signal quality by including a weighted signal average in computations that calculate a regenerated signal's sampling values is presented. Secondary signal lobe values are removed from an original signal during signal re-sampling computations in order to minimize signal re-sampling memory requirements. A weighed signal average is included in signal re-sampling computations in order improve signal quality that was degraded due to the removal of the secondary signal lobe values. Weighted signal averages are calculated using error function values that are included in an error function. Each error function value corresponds to the distance between sample points of an original signal and the regenerated signal. The error function value is combined with the original signal's average signal value to produce a weighed signal average.

Abstract: Methods and systems are provided for synchronizing various time-stamped data streams. The data streams can be synchronized to another data stream or to a point of reference such as a reference clock. In one embodiment, synchronization processing takes place in association with a filter graph comprising multiple filters. The filter graph is configured to process multiple timestamped data streams for rendering the data streams in accordance with data stream timestamps. A synchronization module is provided and is associated with the filter graph queries individual filters of the filter graph to ascertain input timestamp-to-output timestamp mappings. The module computes adjustments that are to be made to output time stamps in order to synchronize the data streams, and then instructs queried filters to adjust their output timestamps in accordance with its adjustment computations.

Abstract: A variable gain amplifier circuit using a variable impedance circuit, includes an input terminal, an operational amplifier, a first variable impedance connected with the input terminal and the operational amplifier, a second variable impedance connected with a reverse input terminal of the operational amplifier and an output terminal of the operational amplifier, a third variable impedance whose first end is connected with the reverse input terminal of the operational amplifier, a fourth variable impedance whose first end is connected with the input terminal and second end is connected with a second end of the third variable impedance, and a fifth variable impedance whose first end is connected with the second end of the third variable impedance and second end is connected with the output terminal of the operational amplifier, wherein the first variable impedance, the second variable impedance, and the third variable impedance are controlled in accordance with an upper bit group, and the fourth variable imped

Abstract: A temperature compensated amplifier with variable gain and to a radio device having an amplifier according to it. The gain control and temperature compensation of a differential amplifier (210) are implemented by a control circuit (220), which has a balanced and differential output (V1, V2). The output voltage of the control circuit, or the control voltage, is arranged to be proportional to difference between two source currents (IGT1, IGT2), which difference can be varied on both sides of zero. The output of the control circuit is connected to the bases of the differential pair (Q1, Q2) of the variable gain amplifier, whereupon the ratio of the output current (iout) to the input current (iin) of the pair becomes dependent on the control voltage. This is arranged to be proportional to the absolute temperature, too. A temperature change then changes the control voltage the more the higher the control voltage is.

Abstract: Methods and systems are provided for synchronizing various time-stamped data streams. The data streams can be synchronized to another data stream or to a point of reference such as a reference clock. In one embodiment, synchronization processing takes place in association with a filter graph comprising multiple filters. The filter graph is configured to process multiple timestamped data streams for rendering the data streams in accordance with data stream timestamps. A synchronization module is provided and is associated with the filter graph queries individual filters of the filter graph to ascertain input timestamp-to-output timestamp mappings. The module computes adjustments that are to be made to output timestamps in order to synchronize the data streams, and then instructs queried filters to adjust their output timestamps in accordance with its adjustment computations.

Abstract: An A/D-conversion circuit is provided that includes: a counter, which outputs a count value CT; a voltage generation circuit, which generates a monotonically increasing or monotonically decreasing analog voltage AV1; a comparator, which compares the analog voltage AV1 with an analog voltage AV2 to which A/D conversion is conducted, and outputs an signal CQ according to the comparison result; a digital filter circuit, which conducts digital filtering processing to the signal CQ and outputs a signal DQ; and a count value hold circuit EFF, which holds the count value CT from the counter based on the signal DQ. The digital filter includes hold circuits FF1 to FF3 and changes the voltage level of the signal DQ, when a pattern of the output signals Q1 to Q3 thereof matches a predetermined pattern.

Abstract: The present invention correctly decodes data encoded with a variable-length encoding method that improves the compression ratio. The variable-length encoding method encodes a unit data composed of a plurality of sub-data while referencing a parameter table, and includes: an initialization step in which the parameter table is set to initial values; a parameter table information encoding step in which information related to the initialized parameter table is encoded; a parameter obtaining step in which encoding parameters to be used in the encoding of sub-data are obtained from the parameter table; a sub-data encoding step in which variable-length encoding of the sub-data is performed with reference to the obtained encoding parameters; and an encoded information placement step in which the encoded information is placed in a position in which the information can be obtained before the encoded unit data.

Abstract: An all-optical linear feedback circuit for use, for example, as a maximal length pseudo random bit sequence generator includes an all-optical logic circuit that is capable of generating 2N?1 bit maximal length pseudo random bit sequences on an optical channel at high data rates e.g. 80 Gbit/s. In the pseudo random bit sequence generator of the present invention, intensity-dependent phase modulation of at least one included semiconductor optical amplifier (SOA) is implemented. The maximum data rate is limited by the fast gain recovery time of the carriers in the SOA. An optical logic gate of the pseudo random bit sequence generator of the present invention may be constructed using various nonlinear elements that provide ultra-fast intensity-dependent phase modulation.