Abstract: There is provided an apparatus and method, the apparatus comprising a power input and a switch isolation circuit to provide isolation between the power input and a protected switch responsive to a timing signal. The switch isolation circuit comprises a switch isolation charge store, and a buffer circuit to receive power from the switch isolation charge store and coupled between the timing signal and the protected switch. The switch isolation circuit is configured to, in response to the timing signal having the first value, operate in a powered mode in which the switch isolation charge store receives power from the power input; and, in response to the timing signal having the second value, operate in an isolation mode in which the switch isolation charge store is isolated from the power input.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: A method includes pre-charging a parasitic capacitance of a control node that is coupled to a control terminal of first and second transistors that have respective current paths that form a switched current path coupled between a load node and a storage node. Pre-charging the parasitic capacitance includes: making conductive a first auxiliary transistor that has a current path coupled between the storage node and the control node, or making conductive a second auxiliary transistor that has a current path coupled between the load node and the control node. The method further includes, after pre-charging the parasitic capacitance, making the switched current path conductive to couple the load node to the storage node.

Abstract: A temperature sensor arrangement (10), including a bandgap voltage generator (12), which is configured to provide an output voltage (Vbg); at least one semiconductor junction (14) for temperature sensing, which is biased by a biasing current flowing through said semiconductor junction (14); and at least one poly-resistor (Rb3) which is connected between the output (23) of the bandgap voltage generator (12) and the semiconductor junction (14), thereby providing said biasing current from the bandgap voltage generator (12) to the semiconductor junction (14).

Abstract: A communication system includes a transmission line and a reception coupler that couples to the transmission line in an electromagnetic field and moves along the transmission line, wherein the reception coupler has end parts narrower than other parts with respect to a transmission direction of the transmission line.

Abstract: A power detector circuit that rejects the common mode portion of a differential signal is disclosed. The circuit includes a differential input having first and second input nodes. Differential and common mode circuit paths are coupled to the differential input. The common mode circuit path includes first and second capacitors coupled to respective first terminals of first and second input nodes of the differential input. The second terminal of each of the first and second capacitors is coupled to a gate terminal of a first bias transistor. The common mode circuit path is configured to reject a common mode portion of a differential input signal provided to the differential input such that a differential output signal is indicative of an amount of power of a differential portion of the differential input signal.

Abstract: A voltage-divider circuit, including: a network of discrete resistors defining T tiers of resistors, where T?2, the T tiers comprising first and subsequent tiers, the Xth tier including at least one Xth-tier resistor where X=1, and the Xth tier including at least two Xth-tier resistors for each value of X in the range 2?X?T, wherein, for each value of X in the range 1?X<T: each Xth-tier resistor is connected between a pair of nodes of the voltage-divider circuit at which a relatively high and low voltage signal are provided, respectively; at least one Xth-tier resistor is implemented as a subdivision network of discrete resistors; and for each Xth-tier resistor implemented as a subdivision network, that subdivision network includes a main resistor connected in series with a corresponding auxiliary resistor, that main resistor implemented as a base resistor connected in parallel with a series connection of a plurality of X+1th-tier resistors.

Abstract: Aspects of the present disclosure are directed toward systems and methods for detecting force applied to a distal tip of a medical catheter. A medical catheter includes a deformable body near a distal tip of the catheter that deforms in response to a force applied at the distal tip, and a sensor detects various components of the deflection. Processor circuitry may then, based on the detected components of the deformation, determine a force applied to the distal tip of the catheter.

Abstract: A driver circuit comprising a differential operational amplifier configured to receive an input voltage and produce a differential output voltage based at least in part on the input voltage. The differential output voltage can be produced for a receiver circuit that is communicatively coupled to the driver circuit.

Abstract: Connectors for a networking device may be provided. A networking device may comprise a first plurality of switch bars each comprising a first switch type arranged parallel to one another, a second plurality of switch bars each comprising a second switch type arranged parallel to one another, and a third plurality of switch bars each comprising a third switch type arranged parallel to one another. The first plurality of switch bars, the second plurality of switch bars, and the third plurality of switch bars may be arranged orthogonally. A first one of the first plurality of switch bars may be connected to a first one of the second plurality of switch bars via a retractable mechanical connector mechanism.

Abstract: A homeostatic circuit for neural networks includes a feedback circuit, a first electronic switch, a synapse circuit, a second electronic switch, a third electronic switch and a first capacitor. The feedback circuit is configured to receive the total synaptic driving current and output a feedback voltage which varies with the total synaptic driving current. The first electronic switch is connected with the synapse circuit and the second electronic switch and configured to receive the feedback voltage and output a current control signal according to the feedback voltage. The second electronic switch is connected with the synapse circuit and the third electronic switch and configured to output a first voltage signal according to the current control signal. The third electronic switch is configured to adjust the total synaptic driving current in a direction opposite to variation tendency of the total synaptic driving current according to the first voltage signal.

Abstract: A driver circuit includes three sub-circuits. A first sub-circuit is configured to generate a drive current output by the driver circuit through an output node during first and second regions of operation and includes: a diode coupled to the output node and a first transistor, and a second transistor coupled to the first transistor and a current mirror. A second sub-circuit is configured to generate the drive current during the first and second and a third region of operation and includes: a third transistor coupled to the output node; and a fourth transistor. A third sub-circuit is configured to generate the drive current during the third region of operation and includes: a current source coupled to the current mirror and a buffer; and a fifth transistor coupled to the third transistor and the fourth transistor and configured to receive an output of the buffer.

Abstract: Various embodiments provide for active suppression circuitry. The active suppression circuitry can be used with a circuit for a memory system, such as a dual data rate (DDR) memory system. For example, some embodiments provide an active suppression integrated circuit. The active suppression integrated circuit can be used by a memory system to efficiently suppress power supply noise caused by resonance of a power delivery network (PDN) of the memory system, thereby improving power integrity of the memory system input/output.

Abstract: A reconfigurable quadrature coupler is disclosed. The reconfigurable quadrature coupler includes an input port transmission line connected to a first port, a coupled port transmission line and a coupled port transformer connected between the coupled port transmission line and a second port. The coupled port transformer is configured to have a selectable second port reflection coefficient. The reconfigurable quadrature coupler further includes an isolation port transmission line and an isolation port transformer connected between the isolation transmission line and a third port. The isolation port transformer is configured to have a selectable third port reflection coefficient. Also included is a through port transmission line and a through port transformer connected between the through port transmission line and a fourth port. The through port transformer is configured to have a selectable fourth port reflection coefficient.

Abstract: An output gain of a latch circuit is increased. The latch circuit includes a first circuit, a second circuit, and first to fourth transistors. The latch circuit includes a first input/output terminal and a second input/output terminal. The first circuit and the second circuit have a function of a current source. In the case where the third transistor is off and the fourth transistor is on, the latch circuit is supplied with a first input signal supplied to the first input/output terminal and a second input signal supplied to the second input/output terminal. In the case where the third transistor is on and the fourth transistor is off, an inverted signal of the first input signal is output to the first input/output terminal of the latch circuit, and an inverted signal of the second input signal is output to the second input/output terminal of the latch circuit. The first circuit and the second circuit increase the output gain of the latch circuit.

Abstract: An operational amplifier 1 comprises transistors Q1 and Q2 forming an input stage, and input resistors R1 and R2 which form a filter together with parasitic capacitors C1 and C2 accompanying the transistors Q1 and Q2. Resistance values R of the resistors R1 and R2 may be set to R=1/(2?·fc·C), where C is the capacitance value of each of the parasitic capacitors C1 and C2, and fc is the target cutoff frequency of the filter. The operational amplifier 1 may also include a power supply resistor R0 which forms a filter together with a parasitic capacitor C0 accompanying a power supply line.

Abstract: A working machine management system includes a working machine having a prime mover and a control unit and a key device which is detachable from the working machine and is used for operating the working machine. The key device stores first authentication information for identifying a drivable working machine and second authentication information necessary for the prime mover to continuously operate. When the key device is attached to the working machine, the control unit confirms validity of the key device based on the first authentication information, compares input information from the outside with the second authentication information to determine whether the prime mover can be operated if the key device is valid, and controls operation of the prime mover according to the determination result.

Abstract: A driver circuit includes: a current-controlling switching element electrically connected to a light emitting element; a differential amplifier circuit including: an output terminal electrically connected to the current-controlling switching element, a first input terminal configured to receive a reference signal as a reference for radiating light with a desired intensity from the light emitting element, and a second input terminal configured to receive a detection signal corresponding to a detection result of a current flowing in the light emitting element, wherein the differential amplifier circuit is configured to control the current flowing in the light emitting element and the current-controlling switching element based on a voltage of the first input terminal and a voltage of the second input terminal; and an adjustment part configured to adjust an overshoot amount of a rising edge of the current flowing in the light emitting element.

Abstract: In a general aspect, a plurality of distinct quantum processor unit (QPU) instances are utilized to execute a quantum computation. Hybrid classical-quantum computing methods and systems are described which utilize the plurality of QPU instances in the execution of quantum computations.

Abstract: Identifying frequencies to be protected at a victim integrated circuit (IC) and sending protection information including the identified frequencies to an aggressor IC. The aggressor IC configures its subsystems or circuits to operate using operating frequencies that prevents spurs that may interfere with the frequencies identified in the protection information. If not all of the frequencies in the protection information can be protected, the aggressor IC selects a subset of the frequencies to be protected. Then, the aggressor IC configures the operating frequencies of its subsystems or circuits so that spurs that they generate do not interfere with the selected frequencies.