Abstract: Apparatus and method for dynamically adjusting a quantum computer clock frequency. For example, one embodiment of an apparatus comprises: a quantum execution unit to execute quantum operations specified by a quantum runtime; a qubit drive controller to translate the quantum operations into physical pulses directed to qubits on a quantum chip at a first cycle frequency; a spin echo sequencer to issue spin echo command sequences to cause the qubit drive controller to generate a sequence of spin echo pulses at the first cycle frequency; and qubit measurement circuitry to measure the qubits and to store qubit timing data for each qubit, the qubit timing data indicating a coherence time or an amount of computational time available for each qubit to perform quantum operations.

Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.

Abstract: A wearable cardiac monitoring device comprises a processor; a electrocardiogram (ECG) signal collecting unit; a photoelectric signal collecting unit; and a power source configured to provide power to the processor, the ECG signal collecting unit and the photoelectric signal collecting unit simultaneously; wherein the processor determines whether the current mode is at a ECG collecting mode or a photoelectric collecting mode; wherein the ECG signal collecting unit collects user's ECG signals in the ECG collecting mode, and the photoelectric signal collecting unit collects photoelectric signals of the user's measured part under the illumination of light.

Abstract: A vehicle, an inductor assembly for power electronics in a vehicle, and a method of providing and cooling an inductor assembly are provided. According to one example, the vehicle is provided with an inductor assembly in a vehicle electrical system with a variable voltage converter (VVC). The inductor assembly includes a core formed from a plurality of core segments spaced apart from one another to define gaps therebetween, with each of the plurality of core segments forming an internal fluid passage extending therethrough. The inductor assembly has a winding surrounding at least one of the plurality of core segments. A fluid system is connected to the core to provide pressurized fluid to the fluid passages of the plurality of core segments to circulate fluid through the core of the inductor assembly.

Abstract: A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.

Abstract: An oscillator circuit is provided. A first and a second cycle generating units, and a first and a second duty generating units are included. An SR latch, receiving outputs the first and second cycle generating units. In the SR latch, an output is provided to the first cycle generating unit and the third duty generating, and a contemporary output is provided to the second cycle generating unit and the second duty generating unit. A logic circuit receives the outputs of the first and the second duty generating units and the output and the contemporary output of the SR latch to generate a clock signal. The first and the second cycle generating units are respectively operated to provide the even and odd cycle times of the clock signal. The first and the second duty generating units are respectively operated to provide the even and odd duties of the clock signal.

Abstract: Apparatus and methods for providing hot-switching immunity for radio frequency switching circuits are disclosed. A radio frequency switching circuit may include both a mechanical switch and a solid-state switch. The mechanical switch may be configurable to couple an output path of a power amplifier to a subsequent component in its transmission path when in a first mechanical switch state and to decouple the output path of the power amplifier from the subsequent component when in a second mechanical switch state. The solid-state switch may be configurable to operatively decouple the mechanical switch from a radio frequency power source when in a first solid-state switch state but not when in a second solid-state switch state. The solid-state switch may be in the first solid-state switch state during transitions of the mechanical switch between the first and second mechanical switch states.

Abstract: A negative impedance circuit includes: a differential circuit stage; a positive feedback path from an output of the differential circuit stage to a first input of the differential circuit stage; and a negative feedback path from the output of the differential circuit stage to a second input of the differential circuit stage. The negative feedback path includes a first transistor, and a unitary gain path from the output of the differential circuit stage to the second input of the differential circuit stage, the unitary gain path coupled to ground via a reference impedance. The positive feedback path includes a second transistor. The first and second transistors are coupled in a current mirror arrangement and have respective control electrodes configured to be driven by the output of the differential circuit stage, where the negative impedance circuit causes a negative impedance at the first input of the differential circuit stage.

Abstract: An analog switch includes an input terminal, an output terminal, a common gate, and a common source. The switch includes a current source which has a first input coupled to a first voltage supply, a control input coupled to receive a gate boost signal, and an output coupled to the common gate. The current source supplies a boost gate current to the common gate during a boost period and supplies a reduced gate current during a second period different than the boost period. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal. The switch includes a Vgs detection circuit which provides the gate boost signal responsive to a conduction of current through the clamp circuit.

Abstract: A power supply system includes a power storage device, a positive electrode-side relay, a negative electrode-side relay, a power control unit that includes a capacitor configured to be pre-charged in response to a system start request and that is connected with the power storage device via the positive electrode-side relay and the negative electrode-side relay, and a control device programmed to close the positive electrode-side relay and the negative electrode-side relay at different timings always or under a predetermined condition in response to the system start request and programmed to change a sequence of closing the positive electrode-side relay and the negative electrode-side relay in accordance with a predetermined restriction. This configuration effectively extends the lives of the positive electrode-side relay and the negative electrode-side relay.

Abstract: A switching driver circuit may have an output stage having an output switch connected between a switching voltage node and an output node. A switch network may control a switching voltage at the switching voltage node so that in one mode the switching voltage node is coupled to a positive voltage and in another mode the switching voltage node is coupled to ground voltage via a first switching path of the switch network. The circuit may also include an n-well switching block operable to, when the first switching voltage node is coupled to a positive voltage, connect the n-well of the first output switch to the switching voltage node, and, when the first switching voltage node is coupled to the ground voltage, connect the n-well of the first output switch to a first ground which is separate to the first switching voltage node and independent of the first switching path.

Abstract: An alternator system includes an alternator with a stator having at least one stationary winding and a rotor with a rotatable field coil for producing alternating current, a main voltage regulator having a main controller and a main power switch configured to control the current through the field coil, a redundant voltage regulator having a redundant controller and a redundant power switch configured to control the current through the field coil. The main power switch, the field coil and the redundant power switch are connected in series, in that order. A power supply for an electrical system includes a battery and the alternator system. A vehicle includes the power supply.

Abstract: An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.

Abstract: An electronic system is disclosed. The system has a differential signal generator configured to generate first and second single ended signals having opposite polarities. The input signal, and the first and second single ended signals transition between a first power voltage and a first ground voltage. The system also has a glitch management circuit configured to generate an output signal based on the first and second single ended signals, where the output signal transitions between a second power voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single ended signals, and to generate first and second intermediate signals. The first and second intermediate signals each transition between the second power voltage and the second ground voltage. The system also has a second latch configured generate the output signal based on the first and second intermediate signals.

Abstract: Disclosed herein is an apparatus that includes a first external terminal supplied with a first power potential, a second external terminal supplied with a second power potential different from the first power potential, a first transistor connected between the first external terminal and an internal power line, a second transistor connected between the second external terminal and the internal power line, and a first circuit configured to turn the first transistor OFF during at least a first period until the second power potential is supplied after the first power potential is supplied.

Abstract: Techniques for implementing robust quantum logic gates are provided and described. In some aspects, a quantum logic gate between a plurality of cavities comprising a first cavity and a second cavity is implemented by performing a first beam splitter operation between the first cavity and the second cavity using a coupling transmon that is dispersively coupled to both the first cavity and the second cavity, and performing a controlled phase shift operation between the second cavity and an ancilla transmon that is dispersively coupled to the second cavity but not dispersively coupled to the first cavity.

Abstract: A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to generate an on-current during a plurality of turn-on switching events to turn on the transistor, wherein the gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage and a second driver configured to, during a first boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage; a measurement circuit configured to measure a transistor parameter indicative of an oscillation of a load current for a turn-on switching event; and a controller configured to receive the measured transistor parameter and regulate a length of the first boost interval based on the measured transistor parameter.

Abstract: A current booster circuit, which can be coupled between a gate driver and a power switch, includes controlled current sources and current sensors to provide a scaled copy of the booster input current at the booster output while operating in a current-gain mode during on-to-off or off-to-on switching periods. During switched-on or switched-off periods, the booster can pull the output to the high or low rail, respectively, through low-impedance circuitry to hold the switch on or off. A voltage and/or current feedback path between the booster output and the booster input permits the booster to control the voltage input during switching operation. The current booster devices and methods can be compatible with both smart and conventional gate drivers of either the voltage-driven or current-driven variety.

Abstract: An active shielding device and method for active shielding are disclosed. The active shielding device includes current sources configured to generate currents, an analog wire shield unit connected to the current sources, a current to voltage converter connected to the analog wire shield unit and configured to generate a voltage in response to the currents that are generated by the current sources, and a voltage comparator connected to the current to voltage converter and configured to compare the voltage that is generated by the current to voltage converters with a reference voltage.

Abstract: A control circuit for a main switch is provided. The control circuit includes an output voltage tracker, a main switch bias generator, and a reference current device. The output voltage tracker is coupled to the main output end and generates a first tracking voltage positively correlated to an output voltage. The main switch bias generator, in response to the first tracking voltage, generates a second tracking voltage substantially equal to the output voltage. The reference current device is coupled to the main switch bias generator and is used to generate a control voltage on a main control end. The reference current device is used to limit the maximum value of the output current. The main switch and a duplicating switching element of the main switch bias generator form a current mirror configuration circuit. The consuming current of the output voltage tracker is positively correlated to the output current.