Patents Examined by Khamdan N. Alrobaie
  • Patent number: 11972790
    Abstract: The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: April 30, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Junpei Sugao
  • Patent number: 11972139
    Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: April 30, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Chun-Wei Tsao, Hsiao-Yi Lin, Wei Lin
  • Patent number: 11972807
    Abstract: Technology is disclosed herein for a memory system that regulates charge pump current during a ramp up of the output voltage. The memory systems operates the charge pump in a current regulation mode while the charge pump output voltage ramps up. After the output voltage crosses a threshold voltage, the charge pump is operated in a voltage regulation mode in which the output voltage is regulated to a target output voltage. In one aspect, the memory system generates a random duty cycle clock in the current regulation mode. The memory system determines a target duty cycle for the random duty cycle clock that will regulate the input current of the charge pump to a target current, given the present output voltage. A clock based on the random duty cycle clock is provided to a clock input of the charge pump to regulate the charge pump current.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: April 30, 2024
    Assignee: SanDisk Technologies LLC
    Inventor: Hiroki Yabe
  • Patent number: 11972828
    Abstract: The repair circuit is disposed in a memory including a normal memory area and a redundant memory area including a target repair unit immediately adjacent to the normal memory area, and the repair circuit being configured to control the target repair unit to repair an abnormal memory cell in the normal memory area. The repair circuit includes: a first control circuit, configured to receive signals at a target number of bits from low to high in a row address, process the received signals to obtain a control result, and output the control result, where the target number is associated with a number of Word Lines in the target repair unit; and a repair determination circuitry, connected to an output terminal of the first control circuit, and configured to receive the control result and output, in combination with the control result, a repair signal indicating whether to perform a repair operation.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: April 30, 2024
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Liang Zhang
  • Patent number: 11967352
    Abstract: A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: April 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungmin You, Wonhyung Song, Hoyoun Kim
  • Patent number: 11961554
    Abstract: A device includes a first power rail for a first power domain and a second power rail for a second power domain. A first circuit block is connected to the first power rail and a second circuit block is connected to the second power rail. The first and second circuit blocks are both connected to a virtual VSS terminal. A footer circuit is connected between the virtual VSS terminal and a ground terminal, and the footer circuit is configured to selectively control a connection between the virtual VSS terminal and the ground terminal.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Kao-Cheng Lin, Wei Min Chan, Yen-Huei Chen
  • Patent number: 11955196
    Abstract: A voltage generating device includes a clock signal generator, a voltage regulator and a pump circuit. The clock signal generator generates a clock signal according to an enable signal. The voltage regulator generates and adjusts a first voltage according to a reference voltage and the enable signal. The pump circuit receives the clock signal, the first voltage and a second voltage, wherein the pump circuit performs a voltage pump operation to generate an output voltage based on the clock signal according to the first voltage and the second voltage. The output voltage equals to a summation of the first voltage and the second voltage.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: April 9, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Jen Chen
  • Patent number: 11948630
    Abstract: Memory cells in a memory array may be configured to include a fuse that will blow in the case of a defective cell. In a 1T-1R memory cell, a fuse may be placed in series with the select element and/or the memory element to counteract a short-circuit in either of these elements. A fuse may be formed by selectively etching a phase-change material (PCM) between two electrodes to leave a cavity. When sufficient energy is applied to the PCM material, the PCM filament will break its crystalline structure and be distributed within the cavity. This prevents the PCM material from recrystallizing. Another fuse may be formed by depositing a material between two electrodes that is doped with mobile ions. When subjected to an excessive signal, the resulting electric field may push these ions permanently towards one of the electrodes, thereby permanently destroying the conductive pathway.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 2, 2024
    Assignee: Applied Materials, Inc.
    Inventor: Federico Nardi
  • Patent number: 11948634
    Abstract: A memory device includes a plurality of memory elements. The memory device additionally includes a first current mirror that when in operation selectively outputs a first current to select a target memory cell as a first memory element of the plurality of memory elements. The memory device further includes a second current mirror that when in operation selectively outputs a second current to select the target memory cell as the first memory element of the plurality of memory elements.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Yen Chun Lee
  • Patent number: 11948661
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Eric J. Stave, Dirgha Khatri, Elancheren Durai, Quincy R. Holton, Timothy M. Hollis, Matthew B. Leslie, Baekkyu Choi, Boe L Holbrook, Yogesh Sharma, Scott R. Cyr
  • Patent number: 11942182
    Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Frederick A. Ware, William N. Ng
  • Patent number: 11935592
    Abstract: A resistive memory device includes a resistive cell connected between a first bit line and a first source line, a reference cell including a reference resistor and connected between a second bit line and a second source line, and a write driver connected to the first bit line or the first source line, connected to the second bit line or the second source line. The write driver includes a comparator configured to compare previous data written in the resistive cell with the target data by comparing a voltage of the first source line with a voltage of the second source line or comparing a voltage of the first bit line with a voltage of the second bit line, and determine whether the target data is written in the resistive cell after comparing the previous data with the target data.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Chankyung Kim
  • Patent number: 11923034
    Abstract: Disclosed herein are related to an integrated circuit including a semiconductor layer. In one aspect, the semiconductor layer includes a first region, a second region, and a third region. The first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. A side of the first region may face a first side of the second region along a first direction. The third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. A side of the third region may face a second side of the second region along the second direction. In one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Sheng Wang, Yangsyu Lin, Kao-Cheng Lin, Cheng Hung Lee, Jonathan Tsung-Yung Chang
  • Patent number: 11923011
    Abstract: A storage device including a nonvolatile memory device that includes a nonvolatile memory cell array including a string including first and second memory cells stacked sequentially, and an OTP memory cell array that stores reference count values, the first and second memory cells respectively connected to first and second word lines; a controller including a processor that generates a read command for the first memory cell; a read level generator including a counter that receives the read command and calculates an off-cell count value of memory cells connected to the second word line, and a comparator that receives a first reference count value from the OTP memory cell array, compares the off-cell count value with the first reference count value to determine a threshold voltage shift of the second memory cell, and determines a read level of the first memory cell based on the threshold voltage shift.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Ho Seo, Suk-Eun Kang, Do Gyeong Lee, Ju Won Lee
  • Patent number: 11922998
    Abstract: A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Atul Katoch, Sahil Preet Singh
  • Patent number: 11915752
    Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Chun-Yun Wu, Chen-Ming Hung
  • Patent number: 11900994
    Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Atuk Katoch
  • Patent number: 11894077
    Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings. A control means is coupled to the word lines and the memory holes and programs the memory cells associated with a first one of the strings in a program operation and acquire a smart verify programming voltage in a smart verify operation including smart verify loops. The control means discards the smart verify programming voltage and determines another smart verify programming voltage in another smart verify operation on the memory cells associated with a second one of the strings in response to a quantity of the smart verify loops needed to complete programming of the memory cells associated with the first one of the strings being outside a predetermined threshold criteria.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: February 6, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ke Zhang, Minna Li, Liang Li
  • Patent number: 11894103
    Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Memory cells coupled with a word line plate, or a subset thereof, may represent a logical page for accessing memory cells. Each word line plate may be coupled with a corresponding word line driver via a respective electrode. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Lorenzo Fratin, Fabio Pellizzer, Enrico Varesi
  • Patent number: 11894102
    Abstract: A duty correction device includes a clock generation circuit, first and second correction pulse generation circuits, and a duty correction circuit. The clock generation circuit generates first to third divided clock signals, each having a phase offset from a reference clock signal. The first correction pulse generation circuit generates a first correction pulse by detecting a phase difference between a delayed clock signal and the first and second divided clock signals. The second correction pulse generation circuit generates a second correction pulse by detecting a phase difference between the second and third divided clock signals. The duty correction circuit checks whether the first and second correction pulses are generated at a preset logic level of the reference clock signal, and reflects the first or second correction pulses in a duty correction operation for the reference clock signal according to a result of the check.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: February 6, 2024
    Assignee: SK hynix Inc.
    Inventors: Chang Kwon Lee, Su Hyun Oh, Jin Hyung Lee