Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.

Abstract: A semiconductor storage device includes a plurality of memory cell transistors, a first wiring electrically connected to the plurality of memory cell transistors, and an erasing circuitry. The erasing circuitry is configured to erase data stored in the memory cell transistors by applying a first voltage to the first wiring, and apply the first voltage such that the first voltage rises to a first value, then falls from the first value to a second value, and is then maintained at the second value.

Abstract: The semiconductor device 1 comprises a processor 2, a memory connected to the processor and a control circuit, and comprises an active operation mode and a standby operation mode. The memory comprises a normal mode and a RS mode lower power consumption than the normal mode. The memory comprises SRAMs 7_0 to 7_5 which includes a mode terminal RS_T supplied with mode instruction signals RS1_0 to RS1_5 specifying the normal mode or the RS mode, respectively. The control circuit supplies the mode instruction signals specifying the normal mode to the mode terminal of the SRAMs 7_0 to 7_2 in transition period which the semiconductor device transitions from the standby operation mode to the active operation mode. And the control circuit supplies the mode instruction signals specifying the normal mode to the mode terminal of the SRAMs 7_3 to 7_5 after transition to the active operation mode.

Abstract: A frequency-voltage conversion circuit includes a constant current source, a first switch connected to an output of the constant current source, a first capacitor connected between the first switch and ground, a second switch connected between a first node that is between the first switch and the first capacitor, and an output node, a third switch connected between the first node and the ground, a fourth switch connected to the output of the constant current source, a second capacitor connected between the fourth switch and the ground, a fifth switch connected between a second node that is between the fourth switch and the second capacitor, and the output node, and a sixth switch connected between the second node and the ground.

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.

Abstract: A device includes a first virtual power line, a second virtual power line, a first delay circuit, and a first wakeup detector. The first virtual power line and the second virtual power line are coupled to a power supply correspondingly through a first group of transistor switches and a second group of transistor switches. The first delay circuit is coupled between gate terminals of the first group of transistor switches and gate terminals in the second group of transistor switches. The first wakeup detector is configured to generate a first trigger signal after receiving a signal from the first delay circuit.

Abstract: Disclosed herein are related to an integrated circuit including a semiconductor layer. In one aspect, the semiconductor layer includes a first region, a second region, and a third region. The first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. A side of the first region may face a first side of the second region along a first direction. The third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. A side of the third region may face a second side of the second region along the second direction. In one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.

Abstract: A memory device is provided that includes at least one resistive memory cell, a negative capacitance field effect transistor (NC-FET) serving as a voltage amplifier, and a switch enable circuit connecting NC-FET to the memory cell. The NC-FET includes a regular FET having a metal gate terminal and a ferroelectric capacitor. The NC-FET gate terminal forms one plate of the ferroelectric (FE) capacitor. The ferroelectric capacitor includes a ferroelectric dielectric material deposited between a formed upper gate conductive contact and he metal gate terminal. To provide further flexibility, a metal layer can be deposited before the deposition of the ferroelectric material to form a MIM-like FE capacitor so that the capacitance of FE capacitance can be independently tuned by choosing the right height (H), width (W), and length (L) to achieve desired matching between |CFE| and Cox where Cox is the gate oxide capacitance and CFE is the ferroelectric capacitance.

Abstract: A first memory cell is coupled to first and third interconnects. A second memory cell is coupled to second and fourth interconnects. A first sense amplifier has a first terminal coupled to the first interconnect and a node of a first potential and a second terminal located close to a node of a second potential and coupled to the third interconnect and has a potential difference between the first and second terminals. A second sense amplifier has a third terminal coupled to the fourth interconnect and a node of a third potential and a fourth terminal located close to a node of a fourth potential and coupled to the second interconnect and has a potential difference between the third and fourth terminals.

Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

Abstract: A receiver including: a data processing circuit, in a training mode, to compare a multi-level signal with first and second voltage signals, and to generate data density signals; a counter circuit to count the data density signals to generate counting values; a control circuit to store, in a register set, a voltage range, counting values corresponding to the voltage range and a control code associated with a first level of the first voltage signal and a second level of the second voltage signal, the voltage range being based on the first and second voltage signals; and a voltage generation circuit, in the training mode, to apply the first and second voltage signals to the data processing circuit and to increase the first level and the second level by a difference between the first and second control signals in response to the control code from the control circuit.

Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.

Abstract: Disclosed are memory structure embodiments including a memory cell and, particularly, an eight-transistor (8T) static random access memory (SRAM) cell with high device density and symmetry. In the 8T SRAM cell, an isolation region is positioned laterally between two semiconductor bodies. Four gate structures traverse the semiconductor bodies. Four p-type transistors, including two p-type pass-gate transistors and two pull-up transistors between the p-type pass-gate transistors, are on one semiconductor body. Four n-type transistors, including two n-type pass-gate transistors and two pull-down transistors between the n-type pass-gate transistors, are on the other. Adjacent p-type and n-type transistors on the different semiconductor bodies share a gate structure.

Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.

Abstract: In a method of resetting a storage device, an internal power supply voltage is generated based on an external power supply voltage. A first reset control signal that is activated when a level of the internal power supply voltage is higher than a reference level. A second reset control signal that is activated after a power-on of the storage device is completed or deactivated after a predetermined delay time from when the external power supply voltage is turned off. A final reset control signal is generated based on the first reset control signal and the second reset control signal. The final reset control signal is activated when at least one of the first and second reset control signals is activated. After the external power supply voltage is turned off, a reset operation is performed when the final reset control signal is activated.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication with a ferroelectric capacitor may be virtually grounded while a voltage is applied to a plate of the ferroelectric capacitor, and the ferroelectric capacitor may be isolated from the virtual ground after a threshold associated with applying the voltage to the plate is reached. A switching component (e.g., a transistor) that is in electronic communication with the digit line and virtual ground may be activated to virtually ground the digit line and deactivated to isolate the digit line from virtual ground.

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.