Abstract: A display device includes a substrate including a display area and a non-display area, a first power supply line in the non-display area and applying a first supply voltage to the display area, and a driving voltage line which is in the display area and connects the display area to the first power supply line. The first power supply line includes a first sub-power supply line, and a second sub-power supply line which is on the first sub-power supply line. The second sub-power supply line includes a same material as the driving voltage line.

Abstract: The invention relates to a radiation-emitting semiconductor chip comprising a semiconductor layer sequence having at least two active regions which generate electromagnetic radiation during operation and at least one reflective outer surface which is arranged to the side of each active region wherein the reflective outer surface includes an angle of at least 35° and at most 55° with a main extension plane of the semiconductor chip. The invention also relates to a method for producing a radiation-emitting semiconductor chip.

Abstract: A photodetector includes a first semiconductor layer, an absorption structure, a second semiconductor layer, and a barrier structure. The absorption structure is located on the first semiconductor layer, and having a first conduction band, a first valence band, and a first band gap. The second semiconductor layer is located on the absorption structure, and having a second conduction band, a second valence band, and a second band gap. The barrier structure is located between the absorption structure and the second semiconductor layer, and having a third conduction band, a third valence band, and a third band gap. The third conduction band is greater than the second conduction band or the third valence band is less than the second valence band.

Abstract: Provided is a semiconductor memory device and method of fabricating the semiconductor memory device. A semiconductor memory device includes a gate stack and a plurality of channel structures. The gate stack includes a plurality of stacked conductive patterns spaced apart from each other. The plurality of the channel structures is formed through the gate stack. Each of the channel structures includes a first channel pillar, a second channel pillar and a gate insulation layer. The first channel pillar is formed through the conductive patterns except for an uppermost conductive pattern. The second channel pillar is formed through the uppermost conductive pattern. The second channel pillar is configured to make contact with the first channel pillar. The gate insulation layer is interposed between the uppermost conductive pattern and the first and second channel pillars.

Abstract: A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate. The pixel circuit includes a driving transistor, a first transistor, and a second transistor; the driving transistor includes a control electrode, a first electrode, and a second electrode; a direction from a first electrode of the first transistor to a second electrode of the first transistor is a first direction, a direction from a first electrode of the second transistor to a second electrode of the second transistor is a second direction, a direction from the first electrode of the driving transistor to the second electrode of the driving transistor is a fourth direction, and at least one of the first direction and the second direction intersects with the fourth direction.

Abstract: The present invention provides a display panel and manufacturing method thereof, the method including following steps: providing a driving backplane and a light-emitting substrate, and bonding the driving backplane and the light-emitting substrate; patterning the light-emitting substrate to form a pixel array; forming a thin film packaging layer on an outside of the pixel array, the thin film packaging layer completely covering the pixel array; forming quantum dots on top of the thin film packaging layer to form a multi-color display; forming a reflective array between two adjacent quantum dots to avoid optical crosstalk between the pixel arrays. The display panel and the method of the present invention break through the physical limit of the high PPI, high-precision metal mask, which can realize the display of 2000 and higher PPI, and can prevent the optical crosstalk between the pixel arrays.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A display panel includes a pad line disposed on a rear surface of a base layer and a connection line disposed on a front surface of the base layer. The pad line and the connection line are connected in an area overlapping a pad hole defined to pass through the base layer, and the pad line is connected to a driving unit on the rear surface of the base layer.

Abstract: A display device may include a first scan connection line connecting a first scan line connected to a first pixel and a first scan output transistor, a first sensing connection line connecting a first sensing line connected to the first pixel and a first sensing output transistor, the first sensing connection line crossing and overlapping the first scan connection line, a second sensing connection line connecting a second sensing line connected to a second pixel adjacent to the first pixel in a first direction and a second sensing output transistor, and a second scan connection line connecting a second scan line connected to the second pixel and a second scan output transistor, the second scan connection line crossing and overlapping the second sensing connection line.

Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.

Abstract: A packaged device (110) includes a substrate (114) and one or more contacts (118) disposed on a side of the substrate (114). Structures of the packaged device (110) define at least in part a recess region (120) that extends from the side of the substrate (114) and through the substrate (114), where one or more contacts (124) of a second hardware interface are disposed in the recess region (120). The one or more contacts (118) of the first hardware interface enable connection of the packaged device (110) to a printed circuit board. The one or more contacts (124) of the second hardware interface enable connection between one or more IC dies of the packaged device (110) and another IC die (150) that is a component of the packaged device (110) or of a different packaged device.

Abstract: A through via structure includes a through via and a capping pattern. The through via includes a metal pattern extending in a vertical direction, and a barrier pattern on a sidewall and a lower surface of the metal pattern. The capping pattern contacts an upper surface of the through via. A lowermost surface of an edge portion of the capping pattern is not higher than a lowermost surface of a central portion of the capping pattern.

Abstract: A display device according to an embodiment of the present invention has a first substrate, a display region provided with a plurality of pixels on the first substrate, each of the plurality of pixels including a light-emitting element, a driving circuit provided along a first direction of the display region on the first substrate, a sealing film covering the display region, and stacking a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer in order from the light-emitting element, a second substrate on the sealing film, a through hole provided in the first substrate, the display region, and the second substrate; and a first region surrounding the through hole.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.

Abstract: An organic light-emitting display panel, a display device, and a method of packaging a display panel are disclosed. The organic light-emitting display panel includes a cover plate, a substrate arranged opposite to the substrate, a packaging layer disposed between the cover plate and the substrate, a touch control circuit formed on the cover plate, touch bonding pins disposed at an edge of the cover plate and coupled to the touch circuit, and multiple shielding terminals disposed on both sides of the touch bonding pins. The touch bonding pins and the shielding terminals are disposed corresponding to the packaging layer. A length of each shielding terminal is consistent with a length of each touch bonding pin. Along a direction of getting away from the touch bonding pins, widths of the plurality of shielding terminals gradually decrease.

Abstract: A display substrate, a display panel, and a display device are disclosed. The display substrate includes first and second display regions and sub-pixels. The sub-pixels are divided into first-type and second-type pixel groups arranged in a second direction. The first-type pixel group includes first and second sub-pixels located in the first and second display regions. The second-type pixel group includes second sub-pixels. The second sub-pixels of at least one of the first-type and the second-type pixel groups are disposed at two sides of the first display region in a first direction. The pixel circuits corresponding to the first and second sub-pixels in one first-type pixel group are connected to one first-type data line. The pixel circuits corresponding to the second sub-pixels in one second-type pixel group are connected to one second-type data line. A power line is disposed below a first-type data line in the first display region.

Abstract: A display device that includes a substrate having a display area configured for displaying an image and a peripheral area positioned outside of the display area. A first thin film transistor is disposed on the display area. A display element is electrically connected to the first thin film transistor. The display element includes a pixel electrode, an intermediate layer, and an opposite electrode. An embedded driving circuit portion is disposed on the peripheral area. The embedded driving circuit portion includes a second thin film transistor. A common voltage supply line is disposed on the peripheral area. The common voltage supply line is positioned closer to the display area than the embedded driving circuit portion. The common voltage supply line is electrically connected to the opposite electrode.

Abstract: A display device includes a substrate including a display area and a peripheral area. A display element is disposed in the display area and is electrically connected to a thin film transistor. A power supply line is disposed in the peripheral area. An insulating layer covers a portion of the power supply line. A barrier layer is disposed on the insulating layer and includes a first side surface facing the display area and a second side surface facing away from the display area. At least one of the first side surface or the second side surface includes a concavo-convex surface. The barrier layer forms a step difference with respect to an upper surface of the insulating layer. An end of the insulating layer is positioned beyond the second side surface of the barrier layer on a side of the barrier layer facing away from the display area.

Abstract: A display device includes a display module including a first base substrate and a pad on a top surface of the first base substrate; a circuit film coupled to a lateral surface of the first base substrate and including a contact pad spaced apart from the pad; and a conductive member on the top surface of the first base substrate and in contact with the pad and the contact pad.

Abstract: In examples, a method of manufacturing a transformer device comprises providing a first magnetic member and providing a laminate member containing primary and secondary transformer windings wound around an orifice extending through the laminate member. The method further comprises positioning a build up film abutting the laminate member. The method also comprises positioning at least a portion of a second magnetic member in the orifice. The method further comprises heat pressing at least one of the first and second magnetic members such that a distance between the first and second magnetic members decreases and such that the build-up film melts, thereby producing a transformer device.