Abstract: Provided is a display device in which a defect by external light reflection is minimized in a non-display area. The display device includes a display panel and a touch unit arranged on the display panel. The display panel may include: a substrate including a display area and a non-display area arranged around the display area; an insulator including a valley portion, the valley portion being defined as an opening arranged along an outer side of the display area in the non-display area; and a display unit arranged in the display area and including a light-emitting element electrically connected to a thin film transistor. The touch unit may include a reflection prevention unit that overlaps the valley portion and is configured to reduce reflectivity of external light.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

Abstract: Embodiments of the present disclosure disclose a display panel and a display device. The display panel includes: a base substrate, a low temperature poly-silicon semiconductor layer, an oxide semiconductor layer and a source-drain metal layer, wherein the source-drain metal layer corresponding to a bending region is provided with a plurality of mutually insulated traces extending in a first direction and arranged in a second direction; an inorganic layer between the base substrate and the source-drain metal layer, wherein the inorganic layer is provided with a groove in the bending region, and the traces are disposed above the groove; and a flexible insulating material between the inorganic layer in the bending region and the traces, wherein the flexible insulating material fills the groove.

Abstract: A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

Abstract: A method includes providing an active pattern and gate metal patterns, and inorganic insulation layers respectively therebetween in a pixel area and each extending to a bending area, providing a first photoresist pattern defining a first opening in the bending area, providing by using the first photoresist pattern, at least one of the inorganic layers in the bending area which is etched, providing a remaining photoresist pattern defining a first remaining opening corresponding to the first opening and a second opening corresponding to the active pattern, and providing by using the remaining photoresist pattern, both a contact hole corresponding to the second opening and exposing the portion of the active pattern to outside the remaining photoresist pattern, and a portion of the base substrate corresponding to the first remaining opening and exposed to outside the remaining photoresist pattern.

Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side and an active area on the second side of the die. The semiconductor packages may also include two or more bumps coupled to two or more die pads on a second side of the die. The semiconductor packages may include an optically transmissive lid coupled to the semiconductor die through an adhesive, two or more bumps, and a first redistribution layer (RDL). The semiconductor package may include a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die. The second RDL may extend to the first side of the semiconductor die. The first RDL may extend to an edge of the semiconductor die.

Abstract: An electronic device may have a hinge that allows the device to be flexed about a bend axis. A display may span the bend axis. To facilitate bending about the bend axis, the display may have layers such as a display cover layer with grooves or other recesses. The recesses form a flexible portion in the display layer. The display layer may be formed from glass or other materials that are transparent. Elastomeric material, fluids, and other materials may be placed in the recesses in the display layer. The material in the display layer may have an index of refraction that is matched to the index of refraction of the display layer. A hinge may be formed between rigid planar layers that are separated by a gap. Flexible layers that lie flush with opposing surfaces of the rigid planar layers may be used to span the gap.

Abstract: A light-emitting panel, a method making same, and a display panel are disclosed in the present disclosure. The light-emitting panel includes a light-emitting board which includes a substrate; a first metal layer disposed on the substrate; a gate insulating layer covering the first metal layer; and a second metal layer on a side of the gate insulating layer away from the first metal layer. The second metal layer includes a connection portion located in the bonding area of the light-emitting board, and a conductive protection layer formed by chemical plating is disposed on a surface of the connection portion.

Abstract: Disclosed in the embodiments of the present disclosure are a display panel and a display device. The display panel includes: a display area and a peripheral area surrounding the display area, the display area includes a first display area and a second display area; a plurality of virtual pixel circuits and a plurality of drive pixel circuits, the plurality of virtual pixel circuits are arranged in the peripheral area, and the plurality of drive pixel circuits are arranged in the second display area; the plurality of first light emitting devices are arranged in the first display area, and the plurality of second light emitting devices are arranged in the second display area; the virtual pixel circuit is electrically connected with the first light emitting device, and the drive pixel circuit is electrically connected with the second light emitting device.

Abstract: This organic-EL display apparatus comprises: a substrate with a drive circuit comprising a thin-film transistor (TFT), a planarizing layer to cover the drive circuit, and an organic light-emitting element formed upon the surface of the planarizing layer facing the opposite direction from the drive circuit. The TFT comprises a drain electrode, a source electrode, and a semiconductor layer that includes regions to be a channel of TFT and partially overlaps with the source and drain electrodes. Respective parts of a first conductor layer forming the drain electrode and a second conductor layer forming the source electrode are arranged in an alternating manner along a prescribed direction, and the region to be the channel is sandwiched between the part of the first conductor layer and the part of the second conductor layer.

Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.

Abstract: An OLED substrate is provided, which comprises a light emitting region and a transparent region, wherein the OLED substrate comprises a substrate and a display layer on the substrate, and a portion of the display layer located in the transparent region has a first hollow part. A method for manufacturing an OLED substrate and a transparent display comprising an OLED substrate are further provided.

Abstract: A display device includes a display panel including a display area and a non-display area surrounding the display area, and a metal wiring layer disposed on at least a portion of the non-display area, an encapsulation substrate disposed on the display panel, a sealing member which is disposed between the display panel and the encapsulation substrate and bonds the display panel to the encapsulation substrate and a first fusion region provided in at least a partial region between the sealing member and the encapsulation substrate, where the first fusion region has no physical boundary, and where at least a portion of the sealing member is disposed on the metal wiring layer in the non-display area, and the first fusion region is separated from the metal wiring layer while overlapping the metal wiring layer in a thickness direction.

Abstract: A semiconductor device includes a memory stack on a substrate, the memory stack including gate electrodes, insulating layers and mold layers, the mold layers being disposed at the same levels as the gate electrodes in a through electrode area, a channel structure extending vertically through the gate electrodes in a cell array area, and a dam structure disposed between the isolation insulating layers and surrounding the through electrode area in a top view. The dam structure includes a dam insulating layer having a dam shape, an inner insulating layer inside the dam insulating layer, and an outer insulating layer outside the dam insulating layer. The inner insulating layer includes first protrusions protruding in a horizontal direction, and the outer insulating layer includes second protrusions protruding in the horizontal direction.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: An array substrate is provided, including a substrate, wherein the substrate is provided with a plurality of electrodes and a plurality of first signal lines, each of the electrodes being correspondingly connected with a first signal line. In some examples, the first signal lines extend in the same direction. In some examples, at least two of the plurality of first signal lines are located in different layers of an insulating spacer from each other. In some examples, orthographic projections on the substrate of at least two of the first signal lines in the different layers at least partially overlap. Accordingly, a light field display device comprising the array substrate is also provided. The array substrate can reduce a light-emitting point size and increase a density distribution of light-emitting points.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a via above a substrate, a dielectric layer over the via, a first source/drain feature above the dielectric layer, a first channel feature above the first source/drain feature, a second source/drain feature above the first channel feature, and a gate line laterally spaced apart from the first source/drain feature, the first channel feature and the second source/drain feature. The gate line passes through the dielectric layer and is on the via.

Abstract: An electro-optical device includes a DA conversion circuit to convert 10 bits of data into an analog voltage output to a data line. The DA conversion circuit includes a first DA conversion circuit to convert upper 5 bits into a voltage and outputs converted voltage to the data line, a second DA conversion circuit to convert lower 5 bits into a voltage and outputs converted voltage to a relay line, and a coupling capacitance including one end electrically coupled to the second DA conversion circuit and another end electrically coupled to the data line, wherein the first DA conversion circuit includes a capacitance element corresponding to the upper 5 bits and is arranged in the Y direction along the data line, and the second DA conversion circuit includes a capacitance element corresponding to the lower 5 bits and is arranged in the Y direction along the data line.