Abstract: The present invention employs a mixture of digital signal processing and analog circuitry to reduce spurious noise in continuous time delta sigma analog-to-digital converters (CT??ADCs). Specifically, a small amount of random additive noise, also referred to as dither, is introduced into the CT??ADC to improve linear behavior by randomizing and de-correlating the quantization noise from the input signal without significantly degrading the SNR performance. In each of the embodiments, digital circuitry is used to generate the desired randomness, de-correlation, and spectral shape of the dither and simple analog circuit blocks are used to appropriately scale and inject the dither into the CT??ADC loop. In one embodiment of the invention, random noise is added to the quantizer input.

Abstract: A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i?1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i?1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.

Abstract: An inverter control microcomputer 10 comprises AD converters 21–23, a selector control circuit 31, and a selector 32. The selector 32 selects three analog signals from among inputted seven analog signals in accordance with control from the selector control circuit 31. A control signal generation section, which comprises a CPU 11 and an inverter control signal generation circuit 17, generates a motor control signal Cntl based on three digital values obtained by the respective AD converters 21–23. By performing AD conversion concurrently for arbitrary three analog signals, it is possible to eliminate a phase shift between the detected analog signals and perform motor control with high precision. Thus, it is possible to detect an analog signal necessary for control of a motor, etc., at an appropriate timing without increasing the number of AD converters.

Abstract: A method can allow a system to selectively control increasing of a bias source in a reference buffer or decreasing impedance looking into a output of the reference buffer for a temporary or selective time period, which can result in an increased overall efficiency of the system. The method can include at least the following steps. A first input signal is received at an input of a reference buffer. A second input signal is received from a load at an output of the reference buffer. A value of a bias source coupled to the output of the reference buffer is modulated, such that a spike of a signal at the output of the reference buffer caused by the second input signal is maintained below a threshold value. Alternatively, an impedance looking into the output of the reference buffer is modulated, such that a spike of a signal at the output of the reference buffer caused by the second input signal is maintained below a threshold value.

Abstract: The domino asynchronous successive approximation (ASA) analog-to-digital converter (ADC) converts an analog signal to an n-bits digital signal. The domino ASA ADC is made out of n-blocks, corresponding to the number of n-bits of the digital output. Each of these n-blocks generates a conversion bit and calibrates all following blocks, comparable to a domino structure. One key advantage of the domino ASA ADC is its modular structure; each block is independent from all others. The unity capacitors used need to be matched only within their specific blocks. The architecture is very flexible; it is possible to increase the resolution by adding more blocks of the same kind. The ASA ADC is very fast, its speed is only limited the RC constants during the sampling and measurement phase and the speed of the comparators used.

Abstract: An apparatus and method for masking interference noise contained in a signal source. According to the present invention, the apparatus comprises: a pseudo random binary sequence generator for generating a digital dither signal; a scrambler for receiving an offset signal and generating a dithered offset signal by scrambling the offset signal with the digital dither signal; a digital-to-analog converter for converting the dithered offset signal into an analog dithered offset signal; a summing device for generating a dithered image signal in response to the analog dithered offset signal and the analog image signal; and an analog-to-digital converter for converting the dithered image signal into the digital image signal.

Abstract: In a data arrangement of a CD-ROM format, data in which DSV control data cannot be placed due to a restriction on the format is followed by control data of two bytes. Main data in which any data cannot be placed is followed by a special control data sequence of two bytes. As a result, after a data sequence of which it is unknown whether the start bit is plus or minus, the sign of the start bit of a diverging control data sequence preceded by the special control data sequence can be kept constant. Consequently, DSV values can be deviated in one direction.

Abstract: System and method for decoding variable-length codes. A variable-length decoder includes an address generator and a local memory unit. The local memory stores a variable-length code look-up table. The local memory can be programmed to include a look-up table supporting substantially any decoding algorithm. In one embodiment, a decoder memory unit and a system memory unit are employed together with the local memory to store a codeword look-up table. The shortest codes are stored in local memory, the next shortest in decoder memory, and the longest codes are stored in system memory. A multistage search algorithm is employed to search for the longest codes. The address generator generates the address of the code table to be searched by adding the value of the bits to be searched to a base address.

Abstract: Code compression techniques and decompression architectures for embedded systems are disclosed, providing good compression ratio while improving decompression time for VLIW instructions and reducing bus power consumption. The invention includes two fixed-to-variable (F2V) length code compression schemes based on a reduced arithmetic code compression algorithm combining arithmetic coding with probability models; a static probability model using static coding and semi-adaptive coding using a Markov model. Multi-bit decompression methods for the F2V techniques are presented, together with a parallel decompression scheme that tags and divides a compressed block into smaller sub-blocks. The Markov model provides better compression ratio, but the static model has a less complicated decompression unit design. The invention also includes two variable-to-fixed (V2F) length coding algorithms, one based on Tunstall coding and another on arithmetic coding.

Abstract: A digitally trimmed current source. The novel current source includes a first circuit for generating a current in response to an applied voltage and a resistance variable in response to a control signal, and a second circuit for supplying the control signal. The first circuit includes a resistive network comprised of a plurality of resistors; a plurality of switches, each switch coupled to one of the resistors and adapted to selectively switch the resistor in and out of the resistive network in response to the control signal; and a transistor adapted to apply a voltage across the resistive network to generate a current.

Abstract: The present invention relates to an arrangement and a method for amplifying high frequency RF signals having amplitude and phase variations. The objective problem of the present invention is to provide an efficient power amplifier for amplifying high frequency RF signals. The object is achieved by introducing a Signal Conditioning Device (SCD) that converts baseband signals SI and SQ into tri-states signals STI, STQ. The tri-states signals STI, STQ are time multiplexed, which results in that a single power amplifier can be used to amplify the signal on the In-phase (I) channel and the signal on the Quadrature (Q) channel. Hence, the present invention does not require a power combiner.

Abstract: A transducer, a method and a coding pattern for determining a kinematic measurable variable are disclosed. A transducer comprises a first device part which is moveable in or through a corresponding device for oil or natural gas production and a second device part which is stationary relative to said first device part. To detect both the directions of movement and the respective position in a simple constructional and inexpensive way without the need for return movement up to ends of the range of movement, the first and/or second device part comprises a coding pattern which is changing along a direction of movement and of which position-specific patterns can be scanned by a scanning means which is arranged on the respective other device part. By scanning such a specific coding pattern during mutual relative movement of said objects or device parts a corresponding scanning signal can then be converted by an evaluation unit into a kinematic measurable variable.

Abstract: A low-voltage differential amplifier circuit is disclosed. The low-voltage differential amplifier circuit includes a first differential amplifier, a second differential amplifier and a summing circuit. The first differential amplifier receives a pair of differential input signals to generate a first output. The second differential amplifier receives the same pair of differential input signals to generate a second output. The summing circuit sums the first output of the first differential amplifier and the second output of the second differential amplifier to provide a common output.

Abstract: The invention concerns a method for determining a numerical value for the duration of a periodically repeating pulsed signal. This method comprises the following steps: a) at time intervals, the period length of the signal is determined; b) at time intervals, a characteristic magnitude for the length of a pulse of that signal is determined; c) a numerical value that characterizes the signal is ascertained from the period length and the characteristic magnitude. Because of its shortness and accuracy, the method is particularly suitable for use in electric motors. A corresponding arrangement is also presented and described.

Abstract: Provided are a rate 13/15 MTR code encoding/decoding method and apparatus. The encoding method includes: generating a predetermined rate-13/15 MTR code in which 13-bit data corresponds to 15-bit data; outputting input 13-bit data as a 15-bit codeword according to the rate-13/15 MTR code; checking whether codewords satisfy a predetermined constraint condition by connecting the 15-bit codeword and a subsequent 15-bit codeword; and converting specific bits of the codewords if the codewords violate the constraint condition and not converting the codewords if the codewords do not violate the constraint condition. The rate-13/15 MTR (j=2, k=8) code includes: 8192 codewords obtained to prevent the number of consecutive transitions from becoming 3 at code boundaries in a modulation coding process. Data can be reliably reproduced with high write density, and a large amount of data can be stored in and reproduced from a magnetic recording information storage medium.

Abstract: Embodiments of the present invention recite a level shifting circuit for high voltage protection. In embodiments of the present invention, the level shifting circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor coupled in a cascode configuration. The circuit further comprises a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor coupled in a cascode configuration. The level shifting circuit further comprises an output coupled with the source of the first transistor, the gate of the seventh transistor, and with the drain of the second transistor. A first inverter is coupled with a second inverter in series and an input signal conveyed to the first inverter dynamically controls the bias level for said second and sixth transistors.

Abstract: A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i?1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i?1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.

Abstract: In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.

Abstract: A method and apparatus are provided for performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions. Each bit has one of first and second complementary logic states. A modified data word is formed by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word. The number of bit positions in the first and second sets is greater than or equal to zero. A result of the Boolean logic tree function is generated based on a pattern of the first and second logic states in the modified data word.

Abstract: Analog-to-digital converter for converting an analog input signal into a digital binary output signal includes a reference unit for generating a thermometric signal based on comparison of the input signal with a reference voltage level, a first logic circuit connected to the reference unit for generating an intermediate signal based on the thermometric signal, and a second logic circuit connected to the first logic circuit for generating the digital binary output signal based on the intermediate signal. The thermometric signal includes a bit word from a first set of bit words and the intermediate signal includes a bit word from a second set of bit words. Bit words from the second set are arranged in rows of a matrix, the sequence of the rows corresponding to unique numbers represented by the bit words. Respective numbers of bit changes in the respective columns of the matrix are at least substantially equal.