Abstract: Present herein is a low memory and MIPS efficient technique for decoding Huffman codes using multi-stage, multi-bits lookup at different levels. A binary tree is cut at levels depending on the quotient of the number of existing nodes and the number of possible nodes.

Abstract: A temperature compensation device for an automatic gain control loop in a receiver of a mobile communication terminal is disclosed. The temperature compensation device comprises a thermistor having a resistance varying with temperature to vary its output voltage, an analog/digital converter for converting the output voltage from the thermistor into a digital signal, and a temperature compensator for outputting a temperature compensation value in response to a digital signal based on a specific temperature variation from the analog/digital converter.

Abstract: A pipelined analog to digital converter (ADC) that is arranged to dynamically adapt its resolution and sampling frequency based on at least one of a determined mode of communication, communication protocol and the strength of a received wireless signal. Since some communication protocols are communicated with a relatively low number of bits (low resolution), the ADC provides for disabling at least a portion of its pipelined stages that provide the higher resolution bits if this type of protocol is detected. By lowering the ADC's resolution and/or frequency for a standby mode communication, a considerable amount of power can be conserved. Similarly, relatively high resolution communication protocol can be processed by the ADC by enabling sufficient pipelined stages to provide a higher resolution (number of bits).

Abstract: A low-voltage differential amplifier circuit is disclosed. The low-voltage differential amplifier circuit includes a first differential amplifier, a second differential amplifier and a summing circuit. The first differential amplifier receives a pair of differential input signals to generate a first output. The second differential amplifier receives the same pair of differential input signals to generate a second output. The summing circuit sums the first output of the first differential amplifier and the second output of the second differential amplifier to provide a common output.

Abstract: Mixed signal processor with noise management. A method for noise management in a mixed signal processor integrated circuit having a digital processing section and an analog section The digital processing section is clocked at a first clock rate to process digital data. When a conversion operation is to be carried out by the analog section, the clocking of the digital processing section is inhibited during at least a portion of the data conversion operation by the analog section to prevent noise from clock transitions in the digital processing section from being injected into the analog section during the at least a portion of th data conversion operation.

Abstract: An integrated digital controller for controlling power electronic devices and method of its use, comprises an analog-to-digital converting scanner module for scanning analog data inputs and used to create digital data correlated with the analog inputs, a loop control module operative to receive the digital data and used for controlling at least one control loop, and a pulse sequence generator (PSG) module used for generating a variety of fast, configurable, event-driven pulse sequences in cooperation with the PSG and scanner modules. The controller comprises optionally a CPU for managing various tasks and coordinate between the modules, means to create the events, and means for configuration and reconfiguration on-the-fly. The controller is preferably integrated in a semiconductor chip.

Abstract: The systematic, and possibly repeated, acquisition of several distinct quantities for exploitation by a user system by utilizing a multiplexer with staged architecture without all inputs hard-wired. Each multiplexer stage is addressed by an elementary counter chained with elementary counters for addressing lower stages. The multiplexer inputs are scanned by regularly incrementing the chain of counters. If no precaution is taken, all the multiplexer inputs are scanned without considering their possible absences. To remedy this drawback a first elementary counter addresses the first stage of adjustable counting capacity switches, the elementary counters can address intermediate stages of the switches with controllable shunting circuits, and a global counter is reconfigured, at the end of each counting cycle of the first elementary counter, by commands adjusting the first elementary counter capacity, and activating or inhibiting the shunting circuits.

Abstract: A system for gray-code counting in an integrated circuit such as a programmable logic device uses a binary adder coupled to a binary counter output and to a selected binary offset value. The binary adder provides a binary sum that is converted to a gray code value by a binary-to-gray converter. The gray code value represents the binary sum output.

Abstract: In an A/D conversion control apparatus for use in an electronic controller such as an engine ECU of a vehicle, each of successive sets of A/D converted values of an analog signal (each set comprising 3 or more values) is processed to obtain a median value of the set, and the median values are subjected to digital smoothing processing to obtain successive final result values, with effects of noise contained in the analog signal being effectively excluded. The final result values are suitable as control data, supplied to a control device such as a microcomputer of an ECU.

Abstract: A digital-to-analog converter circuit for a subscriber line analog front end includes a differential amplifier, switch circuitry, and first and second current steering digital-to-analog converters (DAC), each DAC having a first and second output forming a differential DAC output. The switch circuitry couples the differential output of at most a selected one of the first and second DACs to a pair of switch nodes. When the differential output of the selected DAC is coupled to the pair of switch nodes, the differential output of the other DAC is shorted. A differential input of the differential amplifier is communicatively coupled to the pair of switch nodes. A differential output of the differential amplifier is coupled to drive a tip line and a ring line of a subscriber line. In various embodiments, the DACs, switch circuitry, and differential amplifier reside on the same semiconductor substrate.

Abstract: A signal conditioning system includes first and second converters coupled to a random clock which provides a random sampling rate. Corresponding offset sensor coupled with the first and second converters sense and adjust an offset signal difference. A gain sensor is coupled with the first and second converters to sense a gain difference between the first and second converters and a gain corrector is coupled with the gain sensor to adjust the gain difference.

Abstract: A system and apparatus for discrete PLC control using word sequences in a data table for controlling a device on an assembly line. The data table contains sequencing information which defines, for each station on the line, a series of operations with corresponding setup and operation parameters. By placing the sequencing information in a data table, programming or changing the series of operations for a PLC is made much more simple and efficient.

Abstract: A data dependent scrambler (DDS) for a communications channel that transmits a user data sequence having a plurality of symbols includes a scrambler that generates a scrambled user data sequence that is based on the user data sequence and a seed. A first encoder selectively interleaves adjacent symbols in the scrambled user data sequence if an all-zero symbol is produced by bit interleaving. The first encoder identifies a pivot bit that is adjacent to the all-zero symbol if interleaving is performed and replaces the all-zero symbol with an all-one symbol if the pivot bit is zero.

Abstract: A transmitter circuit (10) includes a phase shifter (20) that receives phase shift compensation and timing data (40), and an amplifier (30) that receives a control signal (70) to initiate an efficiency enhancement technique. The phase shifter (20) receives the phase shift compensation and timing data (40), and the amplifier (30) receives the control signal (70) at a pre-defined relative time such that the compensation phase shift by the phase shifter (20) compensates for a pre-determined phase change in the amplifier (30) to produce an RF output signal (80) with a reduced predicted phase change.

Abstract: The invention relates to a method, mixed signal integrated circuit, mobile communication device, system and computer program for controlling an analog-to-digital converter.

Abstract: A method for providing a digital current signal from an analog armature current signal of a motor. The method includes subjecting the analog current signal to an analog-to-digital conversion to produce a first digital current signal having current ripples for each current ripple of the analog current signal. During start-up and run-down motor operation phases, the analog current signal is sampled at a sampling rate which is greater than an expected rate of the current ripples of the analog current signal to produce a second digital current signal having current ripples for each current ripple of the analog current signal during the start-up and run-down motor operation phases. The current ripples of the first and second digital current signals are then compared. The current ripples of the second digital current signal which are in non-conformance with the current ripples of the first digital current signal are evaluated.

Abstract: A D/A converter includes a ??modulator applying Delta-Sigma modulation to a digital signal in order to generate a code sequence, and first and second post-filters as a first-order analog low-pass filter, respectively, which is connected in cascade to the subsequent stage of the modulator, in which low-pass filtering on the code sequence is executed so as to output an analog signal. The post-filter is set to have a cutoff frequency which falls in the frequency range from fca to fHa, where the fca is a cutoff frequecy of the post-filter 11 and the fHa is a maximum frequency thereof. Since the respective attenuation characteristics of post-filters are synthesized, an overall attenuation characteristic between the both filters is able to have the characteristics of a desired second-order filter.

Abstract: A device for a coaxial connection that is intended to connect a coaxial cable (6) to the conductive pattern (3a) of a circuit board and contains an outer conductor (1) with an inner conductor (4) that is insulated relative thereto. The device contains a longitudinal coupling element (8) that is axially slidably mounted in a recess (4a) in the inner conductor (4;6a) and arranged so as to be in capacitive communication with the inner conductor (4;6a) and connected to the conductive pattern (3a). A layer (7) of insulating material is arranged between the coupling element (8) and the recess (4a).

Abstract: A method of implementing bi-directional level translation in an information handling system includes coupling a first device port via a first resistor to a first voltage. A second device port is coupled via a second resistor to a second voltage different from the first voltage. Lastly, a single bipolar junction transistor (BJT) couples the first device port to the second device port, the single bipolar junction transistor including an emitter coupled to the first device port, a base coupled via a third resistor to the first voltage, and a collector coupled to the second device port, wherein the bipolar junction transistor operates as a bi-directional level translator between the first and second device ports.

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a separate acquisition engine is used which includes a sample reducer for combining samples of a received signal for correlation with a locally generated version of a GPS code. A serial to parallel converter converts the reduced samples to parallel words which are correlated in parallel with locally generated words of the GPS code.