Abstract: The data compressor utilizes a plurality of subdictionaries arranged in levels for storing strings of data characters. The subdictionary at the first level stores two character strings and a subdictionary at a subsequent level stores strings that are one character longer than the strings stored in the subdictionary at the level prior thereto. A plurality of data characters are fetched from the input into an input buffer and applied to the respective levels. The subdictionary at a level is searched for the string comprising the string matched at the prior level extended by the fetched character applied to the level. The string code of a string matched at a level is cascaded to the next level. The longest match with the fetched characters is determined by one of the fetched characters resulting in a mismatch at one of the levels. The string code associated with the longest match is output.

Abstract: The invention relates to an amplification device AD, comprising a first and a second amplifier AMP1 and AMP2, arranged in cascade, each amplifier being provided with a feedback loop Zi (where i=1 or 2) and having a gain proper Gi equal to Ai/(1+Ai.Zi). In accordance with the invention, the value of the inverse of the gain proper Gi of the first amplifier AMP1 is substantially equal to three times the value of the inverse of the gain proper G2 of the second amplifier AMP2 raised to the power of three: (1/G1)=3/(G2)3. Such a choice provides the amplification device AD with an optimum linearity.

Abstract: A GSM system and an EDGE system much different in gain are incorporated into a single high frequency power amplifier module. In a high frequency power amplifier module having a multi-stage amplifying configuration, which is used in a GSM mode and an EDGE mode according to switching, a first-stage amplifier comprises a dual gate MOSFET. In the EDGE mode, an APC signal or a selected and fixed potential is supplied to a first gate electrode of the dual gate MOSFET. Further, Vgs (Vgs1, Vgs2 and Vgs3) of respective transistors of from a first stage to a third stage are fixed in potential form or supplied as APC signals, and the gain in the EDGE mode is matched with that in the GSM mode, whereby the generation of noise is reduced.

Abstract: A method of selectively reducing the impedance presented to the load of a reactive impedance transformation amplifier output stage reduces distortion caused by load reactance. A control circuit is interconnected to a gated switch on at least one side of the load, and the switch is controlled to shunt back-EMF from the load. In one embodiment, the shunting action is initiated when the released energy would approach zero with a purely resistive load. Since the delay time may be a function of energy released, the delay from energy release to shunt initiation is optimally a function of the energy storage time of the inductor. In the event that this energy storage time is regulated using feedback, the shunt delay should be as well regulated, to accentuate the regulatory action. In a more comprehensive embodiment, the amplifier output polarity is inverted and its output caused to be a function of the positive error in the circumstance of a substantial positive error, such as that caused by an inductive load.

Abstract: The present invention provides an high beta, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage over conventional methods disclosed is up to &bgr;2 rather than a single beta. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123). The output of the disclosed operational amplifier output stage takes the form: &dgr;Io≈&bgr;n*&bgr;p*&dgr;Iin. When used with a localized feedback circuitry, speed performance is increased and bandwidth is extended.

Abstract: An apparatus comprising a reference generation circuit and a modulator. The reference generation circuit, may be configured to generate a first one or more reference voltages and a second one or more reference voltages. The modulator may be configured to present an output signal in response to an input signal, the first reference voltages and the second reference voltages. A gain between the output signal and the input signal may be set by a capacitor ratio in said modulator.

Abstract: Microelectromechanical resonators that can be fabricated on a semiconductor die by processes normally used in fabricating microelectronics (e.g., CMOS) circuits are provided. The resonators comprises at least two vibratable members that are closely spaced relative to a wavelength associated with their vibrating frequency, and driven to vibrate one-half a vibration period out of phase with each other, i.e. to mirror each others motion. Driving the vibratable members as stated leads to destructive interference effects that suppress leakage of acoustic energy from the vibratable members into the die, and improve the Q-factor of the resonator. Vibratable members in the form of vibratable plates that are formed by deep anisotropic etching one or more trenches in the die are disclosed. Embodiments in which two sets of vibratable plates are spaced by ½ the aforementioned wavelength to further suppress acoustic energy leakage, and improve the Q-factor of the resonator are disclosed.

Abstract: A wireless communication device (100) may include a transmitter (108), a memory (104), an analog-to-digital converter (128), an audio playback system (124) and other features. A dynamic range controller (130) selectively generates control signals to adjust, at least in part, the operational dynamic range of the analog-to-digital converter (128) for analog signals received by the a transmitter (108) or stored in the memory (104). The selection of dynamic range is based on identifying a characteristic. In one embodiment, the control signals are used to selectively operate the analog-to-digital converter (128) at a particular dynamic range based on a sampling rate set by the remote location or by the user.

Abstract: An offset calibration system includes an analog to digital converter having a first full-scale range with a first offset compensation circuit; a digital to analog converter having a second full-scale range with a second offset compensation circuit; the digital to analog converter having its output connected to the input of the analog to digital converter during calibration of the digital to analog converter; and a range adjustment circuit for accumulating a predetermined number of analog to digital output values and dividing the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit.

Abstract: A flash analog to digital converter includes a reference ladder, consisting primarily of resistors, a plurality of comparators, each coupled to a different reference voltage on the reference ladder (the comparators compare a received voltage with a reference voltage level developed across corresponding resistor or group of resistors), and a variable power source coupled to the reference ladder for varying the reference levels generated from the ladder. The structure includes a fixed (or variable) gain driver supplying the received signal voltage to the bank of comparators. The variable power source can be an adjustable current source or an adjustable voltage source. The comparators can be single-ended comparators or differential comparators.

Abstract: A circuit and method is provided that provides an amplification stage to a comparator device that matches transistor transconductances to provide adequate amplification and employs diode coupled transistors to control the common mode output bias voltage. The circuit and method provides for a high gain comparator stage with control over output common mode voltage, while providing rail to rail output swing during differential mode without an external feedback to the comparator device.

Abstract: A SINC filter for an oversampling Sigma-Delta digital to analog converter (OSDAC) having a cascaded construction that results in reduced sensitivity to capacitor mismatch. Specifically, the SINC filter circuit filter may be defined by a transfer function H(z), which is further defined by first constituent transfer functions H1(z) and H2(z). The constituent transfer functions may be implemented in a cascaded fashion. Preferably, one of the cascaded sections includes a resistor string that defines a plurality of reference voltages. A plurality of switching elements are configured to controllably switch these reference voltages to a capacitor of a tap.

Abstract: A modulated signal is connected to a full bridge switching amplifier (16, 18, 28, 30) and is compensated to remove a predetermined frequency and its odd harmonics. The compensation inverts and delays (26) a signal that is connected to a first half of the full bridge and applies the delayed inverted signal to a second half of the full bridge. By delaying by an odd number of half cycles, the carrier and its odd harmonics are cancelled because the same signal exists on both sides of the full bridge output. When these two same signals are subtracted by the full bridge action, the carrier and odd harmonics are suppressed. Spectral nulls may be provided for various signal applications, not just audio, and when various types of modulation techniques are used, such as PWM and PDM.

Abstract: A circuit, for digitizing an analogue signal includes an analogue to digital converter, a clip processor adapted to estimate a value for clipped digital signal samples, and a buffer adapted to dynamically store a plurality of digitized samples produced by the analogue to digital converter. The clip processor is adapted to read digitized samples from the buffer and replace clipped digitized samples with the estimated values, thereby mitigating the effects of clipping in an output of the circuit.

Abstract: A switched-mode power amplifier is configured for performing power amplification of a plurality of signals input thereto and integrally summing (combining) those signals. Conceptually, this is achieved by replacing the center-tapped input winding component of the transformer within a conventional, balanced-type transformer-coupled voltage switching amplifier with separate input components, one for each input signal, in similar manner to the configuration of the input components of a conventional three-port combiner (trifilar). Accordingly, the input winding of the amplifier's transformer is comprised of a plurality of series-coupled windings, one for each of the plurality of input components/signals. In one embodiment, using balanced amplifier input components comprising series-coupled center-tapped windings, the center tap of each input winding is connected to a voltage rail and each terminal end of the winding is driven by an amplifying active device (i.e.

Abstract: It is shown a low noise amplifier comprising a first circuit block suitable for converting a first amplifier input voltage signal into current, a second circuit block adapted to divide the current coming from said first block, said second block being controlled by a second voltage signal, said first and second blocks conferring a variable voltage gain to the amplifier. The amplifier comprises at least one first and at least one second resistors and a feedback network, said at least one first resistor connected with one first output terminal of said second block and with a supply voltage, and said at least one second resistor being connected between said at least one first and at least one second output terminals of said second block, and said feedback network being coupled with said at least one first terminal and with said first circuit block, and said at least one second terminal being coupled with at least one output terminal of said low noise amplifier.

Abstract: An attenuator control circuit for controlling operation of a differential pair attenuator to provide linear in decibels (dB) operation and temperature and process-independent operation. The attenuator control circuit is coupled in parallel with corresponding control input terminals of the attenuator differential pair. The attenuator control circuit also includes a current control circuit that sources a supply current to the control differential pair. The attenuator control circuit also includes an amplifier that controls current through the first current path of the control differential pair to maintain constant total current, so that the first current path exhibits the desired exponential attenuation function. Since the control differential pair is coupled in parallel with the differential pair attenuator, the output current of the differential pair attenuator also exhibits the desired exponential attenuation function.

Abstract: A circuit for widening the stereobase in the reproduction of stereophonic sound signals contains one amplifier (10, 34) each for the stereo signals assigned to the right-hand and left-hand channel. Each amplifier (10, 34) comprises a non-inverting input (16, 36) for the corresponding stereo signal and an inverting input (18, 42) for an output signal fed back via a first resistor (R1, R5) from the amplifier output (20, 40). An ON/OFF connection is provided between the inverting inputs (18, 42) of both amplifiers (10, 34). The connection between the inverting inputs (18, 42) of the two amplifiers (10, 34) is formed by two amplifiers (48, 50) circuited in antiparallel as voltage followers and a second resistor (R8, R9) connected in series with the output of each amplifier (48, 50).

Abstract: An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement.

Abstract: An electronic circuit that converts an analog input to a digital signal includes a series “string” of resistors that provides reference signals with ascending values across the string. The reference signals are organized in banks of reference signals, with each adjacent set sharing a major code boundary. A coarse bank of comparators compare the analog input to the major code boundary reference signals and provide a coarse logic output. Each bank of reference signals has a corresponding bank of switches, with each switch associated with a particular reference signal in the bank. All of the switches in a particular bank are closed or opened in unison when selected. A particular bank is selected based on the coarse logic output signal. The reference values corresponding to the selected bank are coupled to a fine bank of comparators, each fine bank comparator comparing the analog input signal to one of the selected reference values.