Patents Examined by Linh Van Nguyen
  • Patent number: 6844839
    Abstract: Disclosed is a reference voltage generating circuit for a liquid crystal display liquid crystal display.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: January 18, 2005
    Assignee: Boe-Hydis Technology Co., Ltd.
    Inventors: Hwa Jeong Lee, Yong Il Kim
  • Patent number: 6828819
    Abstract: A memory system includes a chipset mounted on a circuit board, and first and second memory module connectors mounted respectively on the circuit board. The first and second memory modules are inserted into the first and second memory module connectors, respectively. The memory system further includes a bus connected to the chipset and the first and second memory module connectors so to create a branch point. Each of the first and second memory modules includes at least one memory device connected to the bus via a stub line and a stub resistor. Impedance of the bus is less than that of the stub line.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: December 7, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myun-Joo Park, Byung-Se So, Jae-Jun Lee
  • Patent number: 6822594
    Abstract: A combination of low order and high order filters and a rule-based 1-bit quantizer with multiple feedback paths and separate quantization output provide stabilization to a delta-sigma modulator during quantizer overload conditions. The 1-bit delta-sigma modulator system combines the superior in-band noise shaping properties of a high order delta-sigma modulator with the stability of a low order delta-sigma modulator to obtain a high order delta-sigma modulator with overload stability. The 1-bit quantizer operates in accordance with a set of primary quantization rules that enables high and low order delta-sigma modulators to work together and remain stable during overload conditions while minimizing performance degradation.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: November 23, 2004
    Assignee: Cirrus Logic, Inc.
    Inventors: John L. Melanson, Kent B. Chambers
  • Patent number: 6816041
    Abstract: A microwave monolithic integrated circuit (MMIC) assembly and related method are disclosed. A dielectric substrate has a surface on which radio frequency circuits and microstrip lines are formed. At least one MMIC chip opening is dimensioned for receiving therethrough a MMIC chip. A metallic carrier is mismatched as to coefficient of thermal expansion to the dielectric substrate and includes a component surface adhesively secured to the dielectric substrate on the surface opposing the radio frequency circuits and microstrip lines. At least one raised pedestal is on the component surface that is positioned at the MMIC chip opening. A MMIC chip is secured on the pedestal and extends through the MMIC chip opening for connection to the radio frequency circuits and microstrip lines. Stress relief portions are formed in the metallic carrier that segment the carrier into subcarriers and provide stress relief during expansion and contraction created by temperature changes.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: November 9, 2004
    Assignee: Xytrans, Inc.
    Inventors: Danny F. Ammar, Gavin Clark
  • Patent number: 6809663
    Abstract: A digital signal modulation method selects a modulation strategy to modulate current M sets of data by determining variations in a digital sum value (DSV) corresponding to the modulated data modulated according to a first modulation strategy from M sets of data ahead of the current M sets of data.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: October 26, 2004
    Assignee: Via Technologies Inc.
    Inventor: Hao-Kuen Su
  • Patent number: 6803824
    Abstract: A method and apparatus for a variable gain cascode amplifier (or attenuator) is disclosed. Embodiments provide for a compensated input impedance. A gain/impedance controller compensates input impedance corresponding to gain adjustments.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: October 12, 2004
    Assignee: Anadigics, Inc.
    Inventors: Hamid Reza Rategh, Payman Hosseinzadeh Shanjani, Ngar Loong Alan Chan, Mehdi Frederik Soltan
  • Patent number: 6801143
    Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: October 5, 2004
    Assignee: Intel Corporation
    Inventors: Ashwani Oberai, Kavitha A. Prasad, Sreenath Kurupati
  • Patent number: 6794941
    Abstract: A gain-controlled amplifier comprises two signal output stages arranged in parallel to drive an output load in series. A maximum-gain stage provides a maximum of signal gain and the other minimum-gain stage fixes the minimum overall amplifier signal gain. Gain-control input signals differentially applied to the two such stages balance the contributions of the respective gain stages delivered to the common output load. In one aspect, a third shunting transistor is used across the minimum-gain stage. In another version, the output load is a tapped resistor and the respective maximum and minimum gain stages drive different taps.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: September 21, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Andreas Wichern, Niels Gabriel
  • Patent number: 6795004
    Abstract: A signal amplifier apparatus adapted for carrying out delta-sigma modulation of an input signal to carry out pulse width modulation (PWM) of that signal, to obtain a PWM signal, and to amplify this PWM signal so that a signal of a predetermined magnitude is obtained, wherein the signal amplifier apparatus includes a correction circuit for correcting an output of a quantizer provided in a delta-sigma modulation device. The correction circuit is installed in a feedback path with respect to the input side from the quantizer or immediately before a pulse width modulator to thereby correct distortion taking place in the amplifier. In addition, the signal amplifier apparatus invention compares PWM signals at the input and the output of the amplifier to correct the output of the quantizer that is provided in the delta-sigma modulation device, so as to cancel distortion taking place in the amplifier in accordance with respective rising time difference and falling time difference to thereby correct distortion.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: September 21, 2004
    Assignee: Sony Corporation
    Inventors: Toshihiko Masuda, Kazunobu Ohkuri
  • Patent number: 6781527
    Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1(b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: August 24, 2004
    Assignee: Samsung Electronics Co., LTD
    Inventors: Jae-seong Shim, Ki-hyun Kim, Hyun-soo Park, Kiu-hae Jung, Iqbal Mahboob
  • Patent number: 6778023
    Abstract: A bandpass filter is tuned by converting the filter into an oscillator using a negative resistance circuit, tuning the oscillator by using conventional tuning techniques such as tuning a varactor via a phase locked loop, sampling and holding the tuning signal and switching off the negative resistance circuit to convert the oscillator back into a bandpass filter.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: August 17, 2004
    Assignee: Nokia Corporation
    Inventor: Kaare Tais Christensen
  • Patent number: 6774668
    Abstract: A programmable integrated circuit is disclosed that includes a nonvolatile memory cell programmed to represent a configuration bit associated with a special purpose function. A volatile memory cell is associated with the nonvolatile memory cell. The integrated circuit includes a logic gate for logically combining states of the volatile and nonvolatile memory cells to selectively enable the special purpose function, even before the volatile memory cell is initialized. In this way, the predetermined function can be executed prior to a complete initialization of the integrated circuit.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: August 10, 2004
    Assignee: Xilinx Inc.
    Inventor: Frank C. Wirtz, II
  • Patent number: 6768427
    Abstract: In one aspect, in a device such as a printer, an encoder system method initializes the system to produce analog output signals that fall outside the detection range of an A/D converter of the system. In another aspect, in a device such as a printer, an encoder system method initializes the system without converting analog signal levels into corresponding digital values.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: July 27, 2004
    Assignee: Lexmark International, Inc.
    Inventors: Christopher A. Adkins, Michael A. Marra, III, Jay W. Vessels, John T. Writt
  • Patent number: 6768430
    Abstract: The present invention is directed to a system and method which expands the applicability of subsampling to a larger range of signal repetition rates while reducing the range over which the sample rate must be tuned to accommodate a given signal. The resulting sample sequences are in the correct order, enabling direct display with an ordinary oscilloscope or other instrumentation. In one embodiment, a technique is used such that decimation of the samples also improves the response characteristics of the sensor. The system and method provides for a number of different procedures for sampling a signal of a given length. All other parameters being the same, the system allows more freedom in selecting the sample rate to correctly sub-sample a repetitive signal.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: July 27, 2004
    Assignee: Agilent Technologies, Inc.
    Inventor: Michael J. Weinstein
  • Patent number: 6765501
    Abstract: A high performance rotary axis. An upper and lower unit are coupled together by a pair of bearings to permit relative rotation between the units. The bearings are biased relative to others along a link to reduce play between the bearings. A processor and sensor provide for detection of relative positions between the units. A floating stop may be provided to permit rotation about the axis in greater than 360°.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: July 20, 2004
    Assignee: NextEngine, Inc.
    Inventors: Mark S. Knighton, Amit Tandon, John Z. Zheng, Basel F. Bahhour, Marc Goldman, David D. Drobnis, Theodore J. Hauser
  • Patent number: 6753733
    Abstract: The invention relates to an amplifier circuit (20) and a method for reducing stray feedback, wherein an additional feedback compensation terminal is provided at the output of the amplifier circuit. A predetermined fraction of the output signal of the amplifier circuit is output at the feedback compensation terminal (RFB) so as to reduce the stray feedback of the output signal. The feedback compensation terminal (RFB) enables a reduction of the stray feedback by providing an additional stray feedback signal which is negatively added at the input of the amplifier circuit (20) to thereby reduce overall stray feedback. The gain may be adjusted once during manufacturing, or each time when operation of the device is initiated. The amplifier circuit (20) may be a transimpedance amplifier for use in a read head of a reproducing device for a record carrier.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: June 22, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Johannus Leopoldus Bakx
  • Patent number: 6747859
    Abstract: A modular feed-though adapter that allows an electrical connection to a power line network adapter without “using up” an electrical outlet is described. In one embodiment, the modular feed-through adapter also provides noise filtering to protect electrical equipment plugged into the feed-through outlet. The noise filtering also protects the power line network data signals from noise generated by the devices plugged into the feed-through adapter. In one embodiment, the network connections provided by the feed-through adapter are low voltage connections, thus allowing the network connections from the feed-through adapter to be safely plugged directly into low-voltage equipment such as computer network cards and the like. In one embodiment, the modular adapter includes a balun to couple network data signals to the power line.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: June 8, 2004
    Assignee: Easyplug Inc.
    Inventors: Alan K. Walbeck, Dan B. Haab, Kevin L. Hurst, Vaughn R. Staheli
  • Patent number: 6738004
    Abstract: A method and system for integrating a mismatch noise shaper into the main loop of a delta-sigma modulator are disclosed. The mismatch noise shaper output is fed back to the summer and is responsive to the mismatch noise shaper. At appropriate times, the mismatch noise shaper selectively overrides the quantizer so that the mismatch noise shaper changes output values of the mismatch noise shaper from values representative of a corresponding output value of the quantizer to other values representative of a different output value of the quantizer. The overriding feature distinguishes the present Invention from a DEM, as the output of a DEM is only a reordering of the same number of elements as its input. The mismatch noise shaper selectively overrides the quantizer when the quantizer output has prevented the mismatch noise shaper from controlling selection of elements at the mismatch noise shaper output for a predetermined time period.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: May 18, 2004
    Assignee: Cirrus Logic, Inc.
    Inventor: John L. Melanson
  • Patent number: 6734751
    Abstract: A center electrode assembly installed in a lumped-constant isolator includes a ferrite member having a substantially rectangular shape and three central conductors. Each of the central conductors includes a grounded leg portion which extends upward from a ground plate provided at the bottom surface of the ferrite along a side surface of the ferrite, which is bent at an upper ridge portion of the ferrite, and which extends on the top surface of the ferrite. The grounded leg portion of each of the central conductors is bent such that the grounded leg portion is substantially perpendicular to the upper ridge portion of the ferrite, and angular points of the central conductors, the angular points determining the crossing angle of the central conductors, are positioned on the top surface of the ferrite.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: May 11, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takashi Kawanami, Keiji Okamura
  • Patent number: 6731167
    Abstract: The number of components of a high frequency power amplifier is reduced. A bias resistance ratio is adjusted in accordance with a change in the threshold voltage Vth of a transistor. A high frequency power amplifier has a plurality of amplifying systems. Each of these systems has an input terminal to which a signal to be amplified is supplied, an output terminal, a bias terminal, a plurality of amplifying stages which are sequentially cascaded between the input and output terminals, and a bias circuit connected to the bias terminal and each of the amplifying stages to apply a bias potential to the amplifying stage. The amplifying stage includes a control terminal for receiving an input signal and the bias potential supplied to the stage and a first terminal for transmitting an output signal of the stage.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: May 4, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masashi Suzuki, Hitoshi Akamine, Tetsuaki Adachi, Takahiro Sato, Masashi Maruyama, Susumu Takada