Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract: A non-reciprocal circuit device includes a lower metal case, a terminal resin case, a central-electrode assembly, an upper metal case, and a permanent magnet. The central-electrode assembly includes a ferrite to which a dc magnetic field is applied by the permanent magnet, and central electrodes disposed around the ferrite. The terminal resin case includes two sets of opposing side walls and a bottom wall, and cut surfaces formed when a lead frame is separated are provided in one set of side walls, respectively. Terminals for surface mounting are provided on another set of side walls which is different from the one set of side walls.

Abstract: A radio frequency amplifier with improved linearity and minimal third-order distortion. The amplifier includes a first transistor having first, second and third terminals with the first terminal being an input terminal and the second terminal being the output terminal and the third terminal being a common terminal. A linearization circuit is included having first and second terminals. The first terminal is connected to the common terminal of the transistor and the second terminal is connected to the input terminal of the transistor. In a specific embodiment, the linearization circuit is implemented as a unity gain buffer with an input terminal connected to the common terminal of the transistor and an output terminal connected to the input terminal of the transistor.

Abstract: A phase shifter includes a first rat-race ring having four ports, an input coupled to a first one of the ports, an output coupled to a second one of the ports, a first resonant circuit coupled to a third one of the ports, and a second resonant circuit coupled to a fourth one of the ports, each of the first and second resonant circuits including a tunable dielectric varactor. The first rat race ring can be connected to another phase shifting stage including a second rat race ring or a digital switched line phase shifter.

Abstract: Differential signals output by a transfer unit of a latch stage are fed back to a comparator stage as negative feedback signals through a feedback circuit including a differential amplifier comprising two transistors. In this configuration, amplitudes of signals supplied to the transfer unit are stabilized by a feedback effect provided by the feedback circuit to become independent of a through-rate of an input signal supplied to the comparator stage. To be more specific, if the through-rate is high, the amplitudes are reduced, but if the through-rate is low, the amplitudes are increased. As a result, variations in sampling delay related to sampling clock signals are suppressed. With this configuration, for example, harmonic distortions in a flash A/D converter are suppressed as well.

Abstract: An integrated analog multiplexer with several multiplexer inputs, a multiplexer output, a switch device and a differential amplifier with an inverting and a non-inverting amplifier input as well as an amplifier output, wherein the amplifier output forms the multiplexer output, the differential amplifier is connected as inverting amplifier by means of a feedback branch from the amplifier output to the inverting amplifier input and the switch device selectively connects one of the multiplexer inputs with the inverting amplifier input.

Abstract: In a level shift circuit according to the invention, either an input signal IN or an inverted input signal XIN, which are input into the gate electrodes of n-type transistors for signal input, is also given to the substrate of that n-type transistor via p-type transistors for substrate bias. When the signal IN or XIN rises and changes, the threshold voltages of the n-type transistors for signal input is lowered due to the substrate bias effect. Consequently, even if the signal IN or XIN has a low voltage level, operation is carried out at high speeds. Also, when either an output signal OUT or an inverted output signal XOUT is changed to a high voltage level, the transistors for substrate bias become non-conducting, and thus the input signal IN or the inverted input signal XIN is not supplied to the substrate of the n-type transistors for signal input other than when the signal is changing. Consequently, a constant passing-through current does not flow to the substrate of these transistors.

Abstract: A method of photonic analog-to-digital conversion including the steps of using an analog signal to modulate a laser, splitting the modulated optical output into 2N paths, attenuating the different paths along a gradient, then splitting each path again and recombining with an adjacent path in such a way that only one path has significant energy. An implementation architecture is also provided which includes a laser source, a modulator for modulating the laser source in accordance with an analog input signal, a first splitter section for splitting the modulated optical output into 2N paths, and for attenuating the different paths along a gradient, an interferometer section for splitting each path again and for recombining the signals in such a way that only one path has significant energy, and a decoder section for outputting a digital word corresponding to the analog input signal.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: The present invention provides a circuit and a method for high speed prescaler circuits which utilize pull-down transistors in the critical feedback path. This invention contains a high speed CMOS dual modulus prescaler circuit made up of data or D-flip flops connected serially where the flip-flop positive output Q of stage N is connected to the D-input of the N+1 flip-flop stage. It is also made up of a pull-down field effect transistor. The invention has a clock input which has a frequency known as a circuit input frequency, Fin. The output of this prescaler circuit has an output frequency, Fout. The frequency division which results from this prescaler circuit is a divide by [2 to the power (n+2)] minus 1 if a mode signal equals 1 as opposed to a divide by [2 to the power (n+2)] counter, which results when the mode signal is low.

Abstract: The variable power supply to an amplifier in an electrical circuit is dynamically controlled through the use of a lookup table responsive to one or more operating conditions of the electrical circuit. The lookup table is indexed by one or more of the operating conditions and the amount of amplification to be applied to an input signal to the amplifier is determined. One embodiment of the invention comprises a television transmitter circuit including a power amplifier circuit capable of amplifying a variable frequency COFDM or 8VSB input signal where the amount of amplification applied to the input signal is dynamically controlled through the use of a lookup table as a function of the frequency of the input signal.

Abstract: An amplifier and bypass switch circuit includes a circuit input, a circuit output, an amplifier and a switching circuit. The amplifier has an amplifier control input, and a first amplifier output. The amplifier control input is connected to the circuit input. The amplifier output is connected to the circuit output. The switching circuit includes a control input, a switch input, a switch output and a phase matching network. The switch output is connected to the circuit output. The switch input is connected to the circuit input. The phase matching network preserves phase information when the amplifier and bypass switch circuit switches between an amplifier mode and a bypass mode.

Abstract: An electricity distribution network for a motor vehicle, the network having at least two pieces of equipment connected to a storage battery, at least one of the pieces of equipment operates in a pulse mode likely to create oscillations in the network at a resonant frequency thereof, the network includes at least one resistive element and capacitor that are associated in series and that are of resistance and capacitance determined so that the resistance of the resistive element is equal to a damping resistance for the network.

Abstract: A high power ferrite microwave phase shifter that is both compact and low cost. The ferrite phase shifter includes a waveguide having a first cylinder and a second cylinder, the radius of the second cylinder being less than the radius of the first cylinder. The second cylinder is disposed within the first cylinder such that the two cylinders have a common axis of symmetry. The waveguide includes a first septum formed as a disk and disposed within the second cylinder. The disk has a pie-shaped aperture formed therethrough and is centrally disposed within the second cylinder so that the two cylinders and the disk share the same axis of symmetry. The second cylinder has an opening formed therethrough that is aligned with the pie-shaped aperture. The waveguide further includes a second septum that extends from the first cylinder to the disk center while bisecting the pie-shaped aperture, thereby separating an input from an output of the ferrite phase shifter.

Abstract: A method for reducing delay variability in a differential receiver includes receiving a plurality of differential input signals, determining a first transition delay time of an output in response to the plurality of differential input signals, determining a second transition delay time of the output in response to the plurality of differential input signals, and modifying capacitance coupled to the output in response to the first transition delay time and to the second transition delay time.

Abstract: A cascaded SAW filter system includes first and second SAW filters (12a, 12b) each including an input transducer (36, 36′) and an output transducer (37, 37′) on a piezoelectric substrate (38, 38′). Group delay and pass band ripples associated with a time spur at TD′ away from the main signal of the second filter (12b) cancel the group delay and pass band ripples associated with a time spur at TD away from the main signal of the first filter (12a) because: 1) the input and output transducers (36′, 37′) of the second filter (12a) are offset from those of the first filter (12a); 2) the center frequency (f0′) of the second filter (12b) is offset from the center frequency (f0) of the first filter (12a); 3) the perturbation region (P1) of the first filter (12a) is different from the perturbation region (P2) of the second filter (12b) or 3) a combination of 1), 2) and/or 3. The associated time spur echo of the cascaded response will also be canceled.

Abstract: A method for recovering a data required to have n consecutive and repetitive bits is disclosed. The data is obtained by converting a sample value sequence into a binary sequence according to a preset value and the data having n−1 consecutive first-level bits and two second-level bits immediately adjacent to two end bits of the n−1 consecutive first-level bits, respectively. The method corrects one of the two second-level bits, which has a corresponding sample value closer to the preset value than the other, into another first-level bit to obtain n consecutive first-level bits. In addition, a device for recovering a data to be decoded is also disclosed.

Abstract: A stacked radio-frequency module is formed by stacking packages each storing MMICs and mounting another package upside down which stores a control circuit for controlling MMICs. The MMICs and control circuits are each sealed by a metal sealing lid within the cavity of each of the packages which are spatially completely separated from each other. Each of the pads for wiring paths for radio-frequency signals and for power supply/control signals and ground pads are provided within each package and at opposing surfaces of packages to be stacked with corresponding pads joined by a gold bump.

Abstract: A first amplified signal is produced at a first amplifier, a second amplified signal is produced at a second amplifier, and a differential signal representing difference between the first amplified signal and the second amplified signal is generated at a subtraction unit receiving the first amplified signal and second amplified signal, the differential signal being a final amplified signal having a final modulated amplitude and a final modulated phase.

Abstract: A dual function superconducting digitizer circuit which can selectively function either as an analog-to-digital converter (ADC) or as a time-to-digital converter (TDC). Superconducting ADCs and TDCs can provide performance far superior to that obtained using conventional electronics by taking advantage of the intrinsic properties—high switching speed, quantum accuracy, dispersion-less transmission lines, radiation hardness, and extremely low power dissipation—of superconductivity. Since both ADC and TDC functions are desired in most measurement systems, a dual-function digitizer is not only more attractive from a system integration perspective but is also more marketable.