Abstract: A semiconductor memory device includes first and second memory cells, adjacent first and second word line connected to gates of the first and second memory cells, respectively, a word line driver for the first and second word lines, a bit line connected to the first and second memory cells, a sense amplifier circuit configured to detect data stored in the memory cells via the bit line and apply a voltage to the bit line, and a control circuit configured to control the word line driver and the sense amplifier circuit to execute a write operation. During a write operation performed on the first memory cell to increase a threshold voltage of the first memory cell to a target state, the control circuit changes the bit line voltage of the bit line according to a difference between the target state and a threshold voltage state of the second memory cell.

Abstract: The present application provides a dual-port SRAM cell and a layout structure thereof, comprises a first and a second NMOS transistors, a first and a second PMOS transistors; the gates of the first and second NMOS transistors and the drains of the first and second PMOS transistors are connected to a word line; the source of the first NMOS transistor is connected to a first bit line; the source of the first PMOS transistor is connected to a second bit line; the source of the second NMOS transistor is connected to a third bit line; the source of the second PMOS transistor is connected to a fourth bit line; the drain of the first NMOS transistor and the gate of the first PMOS transistor are connected to a common input node of a latch.

Abstract: A continuous-time recurrent neural network (CTRNN) is described that exploits the nonlinear dynamics of micro-electro-mechanical system (MEMS) devices to model a neuron in accordance with a neuron rate model that is the basis for dynamic field theory. Each MEMS device in the CTRNN is configured to simulate a neuron population by exploiting the characteristics of bi-stability and hysteresis inherent in certain MEMS device structures. In an embodiment, the MEMS device is a microbeam or cantilevered microbeam device that is excited with an alternating current (AC) voltage at or near an electrical resonance frequency associated with the MEMS device. In another embodiment, the MEMS device is an arched microbeam device that is excited with a direct current voltage and exhibits snap-through behavior due to the physical design of the structure. A CTRNN can be implemented using a number of MEMS devices that are interconnected, the connections associated with varying connection coefficients.

Abstract: An angle sensor generates an angle detection value based on a first and a second detection signal. A correction apparatus performs correction processing for generating a first corrected detection signal by adding a first correction value to the first detection signal and generating a second corrected detection signal by adding a second correction value to the second detection signal. When an angle to be detected varies with a period T and if no correction processing is performed, the angle detection value contains an Nth-order angle error component varying with a period of T/N. Each of the first and second detection signals contains an (N?1)th-order signal error component and an (N+1)th-order signal error component. The order of the first and second correction values is N?1 or N+1.

Abstract: A device may include a current source configured to couple a charged node to a ground voltage to generate a current. The device may include a second circuit coupled to the node and configured to compare, beginning during a first clock cycle of a clock signal and for each clock cycle of a number of clock cycles of the clock signal, the voltage at the node to a reference voltage to generate a result. The device may further include a control unit configured to: detect, upon completion of a subsequent clock cycle of the clock signal, a change in the result; determine, in response to the change in the result, a transition time based on a number of elapsed clock cycles from the first clock cycle to completion of the subsequent clock cycle; and determine a capacitance of the node based on the transition time. Related systems and methods are also described.

Abstract: In various example embodiments, devices, systems, and methods for a waist measuring belt are provided. An example waist measuring belt is made up of a belt buckle frame with attachments for a belt strap. The belt further includes a position measuring module coupled to the belt buckle frame that measures an attachment position of a second end of the belt strap to the belt buckle frame. The belt also includes a tension measuring module coupled to the belt buckle frame that measures a tension through the belt buckle frame and the belt strap. A memory and a wireless communication module attached to the belt may be used to store measurements and communicate with a mobile device or server. In various embodiments, estimated user waist sizes over time using measured values and belt-specific data may be used to estimate a user's waist size and generate a waist size history.

Abstract: A memory controller device includes a delay line circuitry, data sampler circuits, phase detector circuits, and a control logic circuit. The delay line circuitry delays a data strobe signal to generate first to third clock signals, in which the second clock signal is for reading a data signal, and phases of the first to the third clock signals are sequentially differentiated by a predetermined value. The data sampler circuits sample the data signal according to the first to the third clock signals, in order to generate first to third signals. The phase detector circuits compare the first signal with the second signal to generate a first detection signal, and compare the third signal with the second signal to generate a second detection signal. The control logic circuit adjusts the first to the third clock signals according to the first and the second detection signals.

Abstract: It discloses a circuit for reducing a leakage current of a static random access memory (SRAM) memory array and a control method for the same. The circuit includes a memory array power supply voltage control module, a memory array ground terminal voltage control module and a memory array. The present invention controls the voltages on the power supply terminal and the ground terminal of the memory array through the memory array power supply voltage control module and the memory array ground terminal control module, and may reduce the actual data retention voltages of the bitcells, thereby reducing the leakage power of the SRAM in a data retention state. Meanwhile, the present invention implements the function of adjusting the data retention voltage values of the bitcells by controlling different adjustment signals to cope with different design requirements.

Abstract: A reversible memory element is provided. The reversible memory element comprises a reversible memory cell comprising a Josephson junction and a passive inductor. A ballistic interconnect is connected to the reversible memory cell by a bidirectional input/output port. A polarized input fluxon propagating along the ballistic interconnect exchanges polarity with a stationary stored fluxon in the reversible memory cell in response to the input fluxon reflecting off the reversible memory cell.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.

Abstract: A memory system includes a memory device including a first area being refreshed according to a first refresh period and a second area begin refreshed according to a second refresh period longer than the first refresh period. The memory system also includes a memory controller configured to generate a write command and a write data corresponding to a first write request and a first data.

Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a preceding row address from a preceding read operation to determine whether a read operation is a normal read operation or a burst mode read operation. The burst mode address comparator invokes the burst mode despite the presence of an intervening write operation to a row address not equal to the preceding row address.

Abstract: This application relates to a data protection system and protection method of a display apparatus, and the system comprises a memory, a TCON, and a switcher. The switcher selectively outputs a constant potential signal and a read/write control signal to a memory according to a potential change of a control signal. When the switcher transmits and outputs the constant potential signal to the memory, the switcher disconnects an electrical coupling between the read/write control signal and a protection control end. The memory maintains timing control data to be write-protected according to the obtained signal, or switches the timing control data to be readable-and-writable or write-protected.

Abstract: A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.

Abstract: An apparatus includes: a master die; one or more slave dies; a ZQ resister between a first node and a second node coupled to a voltage terminal; a ZQ pad coupled to each of the first node of the ZQ resister, the master die and the one or more slave dies; and a calibration channel electrically coupling the master die and the one or more slave dies, the calibration channel configured to communicate signals between the master die and the one or more slave dies for coordinating access to the ZQ pad across the master die and the one or more slave dies.

Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Abstract: An illustrative battery charging device may identify a battery to be charged, and charge the identified battery using charge settings that are optimized for the identified battery. In some embodiments, the battery charging device may determine the optimized settings based on monitoring charging performance and discharge activities of the battery over time. The battery charging device may exchange data with a battery management service device, such as by exchanging battery health information, battery settings, and/or other data. The battery charging device may determine charge setting and times to charge a battery that is intended to power an unmanned aerial vehicle to complete a flight path.

Abstract: The present invention relates to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. Each bit in each index word is associated with a physical address for a physical word in the emulated EEPROM, and the index word keeps track of which physical word is the current word for a particular logical address. The use of the index word enables a wear leveling algorithm that allows for a programming command to a logical address to result in: (i) skipping the programming operation if the data stored in the current word does not contain a “1” that corresponds to a “0” in the data to be stored, (ii) reprogramming one or more bits of the current word in certain situations, or (iii) shifting to and programming the next physical word in certain situations.

Abstract: Apparatuses and methods for driving word driver lines in a gradual manner are disclosed herein. Word driver lines may be driven to intermediate potentials between high and low potentials. In some examples, the word driver lines may be driven in a step-wise manner. In some examples, the intermediate potential may be a bias voltage. The bias voltage may be provided by a bias voltage generator. One or more enable signals may be used to control the driving of the word driver line. In some examples, an address signal may be used to control the driving of the word driver line. Driving the word driver line in a gradual manner may cause a word line to discharge in a gradual manner in some examples.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.