Abstract: Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Abstract: A method for providing redundancy in a network centric process control system, where at least one node includes at least one control service as well as at least one middleware service for communicating in the process control system, where the control service and middleware service is each a separate executable running in a separate operating system process provided by a real time operating system thereof, wherein a first control service in a first node communicating via a first middleware service and implementing a first control function acts as an active control service for the first control function and a second control service communicating via a second middleware service and implementing the first control function acts as a standby control service for the first control function, the method including performing, by the first control service, the first control function through subscribing, via the first middleware service, to input process data of the first control function and publishing, via the first mid

Abstract: A near memory system is provided for the calculation of a layer in a machine learning application. The near memory system includes an array of memory cells for storing an array of filter weights. A multiply-and-accumulate circuit couples to columns of the array to form the calculation of the layer.

Abstract: The present invention relates to a dynamic random access memory and a programming method therefor with two stages. In a first stage, a capacitor of a memory cell of the dynamic random access memory is broken down, so that the dynamic random access memory becomes a one-time programmable memory. In a second stage, a resistance of the capacitor that is broken down is reduced, so that state data of the memory cell can be more easily interpreted.

Abstract: A memory device is disclosed. The memory device includes a memory array including a first memory cell arranged in a first row and a first column and a second memory cell arranged in the first row and a second column next to the first column. The first memory cell is configured to perform a write operation in response to a first write signal transmitted through a first write word line. The second memory cell is configured to perform the write operation in response to a second write signal transmitted through a second write word line. The second write word line is separated from and next to the first write word line. The first write signal and the second write signal have different logic values.

Abstract: A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

Abstract: Methods and systems include memory devices with multiple memory cells configured to store data. The memory devices also include a cache configured to store at least a portion of the data to provide access to the at least the portion of the data without accessing the multiple memory cells. The memory devices also include control circuitry configured to receive a read command having a target address. Based on the target address, the control circuitry is configured to determine that the at least the portion of the data is present in the cache. Using the cache, the control circuitry also outputs read data from the cache without accessing the plurality of memory cells.

Abstract: The programming techniques include the step of providing a memory device that includes a plurality of memory cells that are divided into at least two groups including a first group and a second group. The first group includes memory cells that are coupled to full select gate drains (SGDs), and the second group includes memory cells that are coupled to partial SGDs. The method continues with the step of applying a programming voltage to a selected word line that includes at least one memory cell of the first group and at least one memory cell of the second group. Simultaneous to the application of the programming voltage, the method continues with applying voltages to bit lines coupled to memory cells. The voltages being determined based on if the memory cells are of the first group or are of the second group.

Abstract: A semiconductor device includes functional circuits electrically coupled to each other and each coupled to a different thermal circuit. The different thermal circuits are configured to maintain different operating temperatures targeted for each corresponding functional circuit. One of the thermal circuits may use a cryogenic liquid to cool the corresponding functional circuit.

Abstract: An artificial neural network circuit includes a crossbar circuit, and a processing circuit. The crossbar circuit transmits a signal between layered neurons of an artificial neural network. The crossbar circuit includes input bars, output bars arranged intersecting the input bars, and memristors. The processing circuit calculates a sum of signals flowing into each of the output bars. The processing circuit calculates, as the sum of the signals, a sum of signals flowing into a plurality of separate output bars and conductance values of the corresponding memristors are set so as to cooperate to give a desired weight to the signal to be transmitted.

Abstract: A computer-implemented method according to one embodiment includes receiving a training data set to be applied to a model; selecting a subset of the training data set as a sample set; for each of a plurality of predetermined augmentations, applying the predetermined augmentation to the sample set to create an augmented sample set, training the model with the augmented sample set, determining a performance of the trained model, and assigning a weight to the predetermined augmentation for the training data set, based on the determined performance; and selecting one or more of the plurality of predetermined augmentations to be applied to the training data set before the training data set is applied to the model, based on the weight assigned to each of the plurality of predetermined augmentations.

Abstract: A semiconductor memory device includes a precharge block, a select block, a peripheral circuit, and control logic. The precharge block is connected to bit lines and includes memory cells in an erase state. The select block shares the bit lines with the precharge block and includes memory cells in a program state. The peripheral circuit performs erase operation on the select block. The control logic controls the peripheral circuit to turn on a first circuit connected to the precharge block and apply first voltage to global lines connected to the first circuit when erase voltage is applied to a source line commonly connected to the precharge block and the select block. The memory cells of the precharge block are turned on by the first voltage applied from the global lines, and the erase voltage applied to the source line is transferred to the bit lines through the precharge block.

Abstract: The present invention relates to a neuromimetic network comprising a set of neurons and a set of synapses, at least one neuron comprising a first stack of superimposed layers, the first stack successively comprising: a first electrode, a first barrier layer made of an electrically insulating material, and a second electrode, the first electrode, the first barrier layer and the second electrode forming a first ferroelectric tunnel junction, at least one synapse comprising a second stack of superimposed layers, the second stack successively comprising: a third electrode, a second barrier layer made of an electrically insulating material, and a fourth electrode, the third electrode, the second barrier layer and the fourth electrode forming a second ferroelectric tunnel junction.

Abstract: A semiconductor memory device according to an embodiment includes a peripheral circuit part supplied with a first voltage, a core circuit part supplied with a second voltage greater than the first voltage, a pre-decoder provided in the peripheral circuit part, input with a signal and outputting a one-hot signal corresponding to the signal, a first wiring provided in the peripheral circuit part, electrically connected to the pre-decoder, and supplied with the one-hot signal, a second wiring provided in the core circuit part, a level shifter provided in the peripheral circuit part, supplied with a first voltage and a second voltage, and transferring the one-hot signal from the first wiring in the peripheral circuit part to the second wiring in the core circuit part, and a memory cell array provided in the core circuit part and operating based on the transferred one-hot signal.

Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

Abstract: A data storage device including a memory device and a memory controller is disclosed. The memory controller including a super block includes a parity controller in communication with a memory device including a plurality of pages and configured to generate a first parity using data to be written to a first group of pages among the plurality of pages, and generate a second parity using data to be written to a second group of pages among the plurality of pages, a write operation controller configured to control the memory device to store the first parity and the second parity, and an error correction circuitry coupled to apply the first parity and the second parity to correct at least one of the plurality of pages arranged to belong to the first group of pages and the second group of pages.

Abstract: Methods and apparatus are disclosed for managing the storage of dynamic neural network data within bit-addressable memory devices, such phase change memory (PCM) arrays or other storage class memory (SCM) arrays. In some examples, a storage controller determines an expected amount of change within data to be updated. If the amount is below a threshold, an In-place Write is performed using bit-addressable writes via individual SET and RESET pulses. Otherwise, a modify version of an In-place Write is performed where a SET pulse is applied to preset a portion of memory to a SET state so that individual bit-addressable writes then may be performed using only RESET pulses to encode the updated data. In other examples, a storage controller separately manages static and dynamic neural network data by storing the static data in a NAND-based memory array and instead storing the dynamic data in a SCM array.

Abstract: A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion amplification circuits for converting currents flowing via the memory elements into voltages, a differential amplifier circuit for performing a differential operation on outputs of two I-V conversion amplification circuits, an A-D converter for performing an A-D conversion on a result of the differential operation, and an output determine that, by referring to input signals of the differential amplifier circuit, determines whether an output signal value of the differential amplifier circuit belongs to an active region or an inactive region. Based on a determination result, the input determiner switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.

Abstract: Distributing multiply-accumulate currents across segment mirrors by providing a circuit including an array of resistive elements, the array including rows and columns and first stage current mirrors, each of the first stage current mirrors being electrically coupled to a segment, wherein the segment comprises a columnar subset of the resistive elements, providing, by the array, a vector of current outputs equal to an analog vector-matrix product between a vector of voltage inputs to the array and a matrix of analog resistive weights within the array, wherein the voltage inputs encode a vector of analog input values, wherein each row of resistive elements corresponds to a specific voltage input, determining a score for each of the rows, determining a ranking of the rows of the array according to the score of each row, and mapping each row to a segment according to the ranking.