Abstract: Techniques to provide for improved (i.e., reduced) power consumption in an exemplary neural network (NN) and/or Deep Neural Network (DNN) environment using data management. Improved power consumption in the NN/DNN may be achieved by reducing a number of bit flips needed to process operands associated with one or more storages. Reducing the number bit flips associated with the NN/DNN may be achieved by multiplying an operand associated with a first storage with a plurality of individual operands associated with a plurality of kernels of the NN/DNN. The operand associated with the first storage may be neuron input data and the plurality of individual operands associated with the second storage may be weight values for multiplication with the neuron input data. The plurality of kernels may be arranged or sorted and subsequently processed in a manner that improves power consumption in the NN/DNN.

Abstract: A read threshold voltage can vary over time due to process variation, data retention issues, and program disturb conditions. A storage system can calibrate the read threshold voltage using data from a decoded codeword read from a wordline in the memory. For example, the storage system can use the data instead of syndrome weight in a bit error rate estimate scan (BES). As another example, the storage system can use the data to generate a bit error rate distribution, which can be used instead of a cell voltage distribution histogram. Using these techniques can help reduce latency and power consumption, increase throughput, and improve quality of service.

Abstract: Examples herein relate to devices that include a strobe tree circuit for capturing data using a memory-sourced strobe. In an example, a device includes a data capture path including first and second flip-flops, and a strobe tree including a comparator and first and second multiplexers. The comparator is configured to output complementary signals on first and second output nodes. First and second selection input nodes of the first multiplexer are connected to the first and second output nodes of the comparator, respectively. First and second selection input nodes of the second multiplexer are connected to the second and first output nodes of the comparator, respectively. The read strobe tree is configured to provide first and second signals output from the first and second multiplexers to first and second nodes, respectively. Clock input nodes of the first and second flip-flops are connected to the first and second nodes, respectively.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes a plurality of memory cells. Each of the plurality of memory cells is connected to one of a plurality of word lines and is arranged in one of a plurality of blocks. Each of the plurality of memory cells is configured to retain a threshold voltage corresponding to one of a plurality of data states. A control circuit is coupled to the plurality of word lines and is configured to detect at least one use characteristic of the memory apparatus. The control circuit adjusts a verify voltage level by one of a plurality of verify level offsets based on the at least one use characteristic that is detected. The verify voltage level is applied to the one of the plurality of word lines selected for programming following an application of a program voltage during a program operation.

Abstract: A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked over the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device via a plurality of through electrodes. In a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes, configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally.

Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.

Abstract: A neural network circuit includes a memory device in which memristors being variable resistance elements are connected in a matrix and serve as memory elements of the memory device. The neural network circuit further includes a voltage application device arranged to apply a bias voltage to the memory device and current-voltage (I-V) conversion amplification circuits arranged to convert currents flowing via the memory elements into voltages and output the voltage. A feedback resistor of a respective I-V conversion amplification circuit includes a memristor. The feedback resistor of a respective I-V conversion amplification circuit and the memory elements acting as an input resistor of the I-V conversion amplification circuit are connected to align a polarity direction of the memristor of the feedback resistor and polarity directions of the memristors of the memory elements acting as the input resistor.

Abstract: A system for training an artificial intelligence (AI) model for an AI chip to implement an AI task may include an AI training unit to train weights of an AI model in floating point, a convolution quantization unit for quantizing the trained weights to a number of quantization levels, and an activation quantization unit for updating the weights of the AI model so that output of the AI model based at least on the updated weights are within a range of activation layers of the AI chip. The updated weights may be stored in fixed point and uploadable to the AI chip. The various units may be configured to account for the hardware constraints in the AI chip to minimize performance degradation when the trained weights are uploaded to the AI chip and expedite training convergence. Forward propagation and backward propagation may be combined in training the AI model.

Abstract: A memory device and a read method thereof are provided. The read method of the memory cell array includes: reading a memory cell array to obtain page data; dividing the page data into a plurality of chunk data; performing a first error correction operation on each of the chunk data in sequence to respectively generate a plurality of first corrected chunk data; performing a second error correction operation on the page data to generate corrected page data; and outputting the corrected chunk data by referring to an indicating signal.

Abstract: In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.

Abstract: A nonvolatile memory device and an operating method are provided. The nonvolatile memory device includes a memory cell array including a plurality of planes, each plane including a plurality of memory blocks, an address decoder connected to the memory cell array, a voltage generator configured to apply an operating voltage to the address decoder, a page buffer circuit including page buffers corresponding to each of the planes, a data input/output circuit connected to the page buffer circuit configured to input and output data and a control unit configured to control the operation of the address decoder, the voltage generator, the page buffer circuit, and the data input/output circuit, wherein the control unit is configured to operate in a multi-operation or a single operation by checking whether a memory block of an access address is a bad block.

Abstract: In one implementation, a method for detecting a configuration of wireless sensors within a vicinity includes a method of assessing wireless sensors in the vicinity of an application computing system. The application computing system is operated in a listen mode to receive and record wireless transmissions produced by one or more wireless sensors producing wireless transmissions in the vicinity of the application computing system. The recorded wireless transmissions are evaluated using a rule set that embodies normal operating characteristics of various types of wireless sensors in an operating environment to generate a conclusion regarding at least one attribute of at least one wireless sensor that produced the recorded wireless transmissions. The generated conclusion can be used so that the at least one wireless sensor is utilized in the application computing system.

Abstract: A memory network can be constructed with at least memory write weightings, memory read weightings and at least one read vector, the memory write weightings parameterizing memory write operations of a neural network to the memory matrix, the memory read weightings parameterizing memory read operations of the neural network from the memory matrix. At least one of the write weightings, the read weightings, or elements of the at least one read vector, can be initialized to have sparsity and/or low discrepancy sampling pattern. The memory network can be trained to perform a task.

Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Abstract: Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data states of the memory cell transistors may be reversed such that the erased state comprises the highest data state corresponding with the highest threshold voltage distribution. To facilitate programming of the memory cell transistors with reversed programmed data states, a non-volatile memory device structure may be used in which the bit line connections to NAND strings comprise direct poly-channel contact to P+ silicon and the source line connections to the NAND strings comprise direct poly-channel contact to N+ silicon.

Abstract: A synapse circuit with an arrayed structured memory for machine learning applications is disclosed. The synapse circuit comprises a controlled variable resistance, a controlled switch connected to a contact terminal of the controlled variable resistance, and a memory cell for storing a weight variable. The memory cell is operatively connected to a control terminal of the controlled switch. A control terminal of the controlled variable resistance is configured for receiving an activation signal. The controlled variable resistance has a first resistance value and a second resistance value substantially larger than the first resistance value. A ratio of the second resistance value to the first resistance value is at least one hundred.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data on which the pattern matching operation is performed may not be output from the memory during the pattern matching operation.

Abstract: An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.