Abstract: An electronic device includes a memory having a plurality of memory rows and a memory refresh functional block that performs a victim row refresh operation. For the victim row refresh operation, the memory refresh functional block selects one or more victim memory rows that may be victims of data corruption caused by repeated memory accesses in a specified group of memory rows near each of the one or more victim memory rows. The memory refresh functional block then individually refreshes each of the one or more victim memory rows.

Abstract: In various example embodiments, devices, systems, and methods for a waist measuring belt are provided. An example waist measuring belt is made up of a belt buckle frame with attachments for a belt strap. The belt further includes a position measuring module coupled to the belt buckle frame that measures an attachment position of a second end of the belt strap to the belt buckle frame. The belt also includes a tension measuring module coupled to the belt buckle frame that measures a tension through the belt buckle frame and the belt strap. A memory and a wireless communication module attached to the belt may be used to store measurements and communicate with a mobile device or server. In various embodiments, estimated user waist sizes over time using measured values and belt-specific data may be used to estimate a user's waist size and generate a waist size history.

Abstract: Methods, systems, and devices for multi-component cell architectures for a memory device are described. A memory device may include self-selecting memory cells that include multiple self-selecting memory components (e.g., multiple layers or other segments of a self-selecting memory material, separated by electrodes). The multiple self-selecting memory components may be configured to collectively store one logic state based on the polarity of a programming pulse applied to the memory cell. The multiple memory component layers may be collectively (concurrently) programmed and read. The multiple self-selecting memory components may increase the size of a read window of the memory cell when compared to a memory cell with a single self-selecting memory component. The read window for the memory cell may correspond to the sum of the read windows of each self-selecting memory component.

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller includes an error correction code (ECC) circuit. The ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes. The memory controller is configured to write second data based on the buffer to the memory device.

Abstract: A semiconductor memory device includes a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal. The signal propagation circuit includes a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit, and further including a terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.

Abstract: A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.

Abstract: The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.

Abstract: Methods, systems, and devices for techniques for low power operation are described. A device may be configurable to operate in a first mode and a second mode, where the first mode may include transmitting using a first modulation scheme having two logic levels and the second mode may include transmitting using a second modulation scheme having three or more (e.g., four) logic levels. The device may identify a data symbol for transmission and select, from the first mode and the second mode, the first modulation scheme for the transmission. In some example, the device may determine which of the two modes to select based on a value stored at a mode register. Here, the value stored by the mode register may indicate to utilize the first modulation scheme associated with the first mode. Thus, the device may transmit the data symbol by a signal modulated by the first modulation scheme.

Abstract: A neuromorphic device includes a memory cell array that includes first memory cells corresponding to a first address and storing first weights and second memory cells corresponding to a second address and storing second weights, and a neuron circuit that includes an integrator summing first read signals from the first memory cells and an activation circuit outputting a first activation signal based on a first sum signal of the first read signals output from the integrator.

Abstract: A method of operating an integrated circuit includes writing data to each memory cell in a first memory cell array, powering off the integrated circuit, powering on the integrated circuit, reading data from each memory cell in the first memory cell array in response to powering on the integrated circuit, and determining whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array. The integrated circuit includes a first memory cell array.

Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

Abstract: Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.

Abstract: According to one embodiment, a memory device includes a memory cell including a resistance change memory element in which a plurality of data values according to resistance are allowed to be set, and a selector element connected to the resistance change memory element in series, a word line supplying a select signal for selecting the resistance change memory element by the selector element to the memory cell, a bit line to which a data signal according to a data value set in the resistance change memory element is read, a load circuit connected to the memory cell in series and functioning as a load, and a comparator circuit which compares a voltage obtained by the load circuit with a plurality of reference voltages.

Abstract: Apparatus including an array of memory cells, and a controller configured to cause the apparatus to determine a first value indicative of a number of memory cells of a plurality of memory cells that are activated in response to a control gate voltage having a particular voltage level, compare the first value to a plurality of second values, and determine an expected data age of the plurality of memory cells or a plurality of read voltages in response to the comparison of the first value to the plurality of second values.

Abstract: A displaying apparatus includes a pixel unit. The pixel unit includes at least one pixel having a light emitting device and a light conversion layer for converting a first wavelength of light of the light emitting device into a second wavelength of light different from the first wavelength; and an insulation layer covers side surfaces of the light emitting device and the light conversion layer.

Abstract: Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the memory device, to perform operations that include, generating a block stripe of the memory device, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and responsive to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe.

Abstract: An in-memory digital processor, Perpetual Digital Perceptron (PDP), is disclosed. The digital in-memory processor of the invention processes the input digital information according to a database of the digital content data stored/hardwired in the Content Read Only Memory (CROM) array and outputs the correspondent digital response data stored/hardwired in the Response Read Only Memory (RROM) array. The PDP is the hardwired digital in-memory processor without re-configuration capability and similar to the instinct functions of biological hardwired brains without re-shaping their neuromorphic structures from training and learning.

Abstract: A spin orbit torque memory device having a vertical transistor structure. The spin orbit torque memory device includes a magnetic memory element such as a magnetic tunnel junction formed on a spin orbit torque layer. The vertical transistor structure selectively provides an electrical current to the spin orbit torque layer to switch a memory state of the magnetic memory element. The vertical transistor structure accommodates the relatively high electrical current needed to provide spin orbit torque switching while also consuming a small amount of wafer real estate. The vertical transistor structure can include a semiconductor pillar structure surrounded by a gate dielectric layer and a gate structure such that the gate dielectric layer separates the gate structure from the semiconductor pillar.

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.