Abstract: A structure includes a semiconductor light emitting device including a light emitting layer disposed between an n-type region and a p-type region. The light emitting layer emits first light of a first peak wavelength. A wavelength-converting material that absorbs the first light and emits second light of a second peak wavelength is disposed in the path of the first light. A filter material that transmits a portion of the first light and absorbs or reflects a portion of the first light is disposed over the wavelength-converting material.

Abstract: A semiconductor component having smooth, void-free conductive layers and a method for manufacturing the semiconductor component. Surface features such as gate structures are formed on a semiconductor substrate. A layer of insulating material is formed on the gate structures and a layer of polysilicon is formed on the layer of insulating material. The layer of polysilicon is annealed in a hydrogen ambient to redistribute the silicon atoms of the polysilicon layer. Redistribution of the atoms fills voids that may be present in the layer of polysilicon and smoothes the surface of the layer of polysilicon. Another layer of polysilicon is formed over the annealed layer of polysilicon. This polysilicon layer is annealed in a hydrogen ambient to redistribute the silicon atoms and smooth the surface of the polysilicon layer, thereby forming a subsequently annealed polysilicon layer. Control gate structures are formed from the subsequently annealed polysilicon layer.

Abstract: A MOSFET device structure and a method of manufacturing the same, in which a photon absorption layer is formed over a gate structure and a substrate in order to avoid plasma induced damage to the gate oxide during high density plasma deposition of a interlayer dielectric layer. The device structure may include an etch stop layer below the photon absorption layer. The photon absorption layer is formed entirely of silicon germanium or it may be a multi-layer formed of a silicon layer and a silicon germanium layer. In the multi-layer structure the silicon germanium layer may be formed on top of the silicon layer or vice-versa. The silicon germanium layer may be formed by implanting germanium ions into a silicon layer or by an epitaxial growth of the silicon germanium alloy layer. In the photon absorption layer the germanium may be substituted by another element whose band gap energy is less than that of silicon.

Abstract: The present invention relates to a method of manufacturing a nitride semiconductor, and, more particularly, a crystal growth method of a nitride semiconductor wherein a nitride semiconductor are grown on a nitride buffer layer including aluminums so that it is possible to improve electrical and crystalline characteristics.

Abstract: A semiconductor device and method of making the same forms a spacer by depositing a spacer layer over a substrate and a gate electrode and forms a protective layer on the spacer layer. The protective layer is dry etched to leave a thin film sidewall on the spacer layer. The spacer layer is then etched, with the protective layer protecting the outer sidewalls of the spacer layer. This etching creates spacers on the gate that have substantially vertical sidewalls that extend parallel to the gate electrode sidewalls. The I-shape of the spacers prevent punch-through during the source/drain ion implantation process, providing an improved source/drain implant dose profile.

Abstract: A thin film transistor substrate of horizontal electric field type includes: a gate line and a first common line formed on a substrate to be in parallel to each other; a data line crossing the gate line and the first common line with a gate insulating film therebetween to define a pixel area; a second common line crossing the first common line having the gate insulating film therebetween; a thin film transistor connected to the gate line and the data line; a common electrode extending from the second common line in said pixel area; a pixel electrode that is parallel to the common electrode and the second common line; a protective film for covering the thin film transistor; a gate pad having a lower gate pad electrode connected to an upper gate pad electrode through a first contact hole; a common pad having a lower common pad electrode connected to an upper common pad electrode through a second contact hole; and a data pad having a lower data pad electrode connected to an upper data pad electrode provided with

Abstract: A method for producing a multi-layer device. The method initially providing a substrate which comprises a support region for supporting an electrical component, then forming an electrically conductive bond layer on a surface of the substrate. The bond is configured to surround the region for supporting the component. The next step in the method is to provide an encasing layer in contact with the bond layer, such that the component is encased between the substrate and the encasing layer. The final step involves bonding the encasing layer to the bond layer to form a sealed cavity which encloses the component. Further, a multi-layer device is provided. The device comprises a substrate, at least one electrical component which is located on the substrate, an electrically conductive bond layer and an encasing layer. The bond layer is formed on the substrate and surrounds the electrical components and the encasing layer is bonded to the bond layer to form a sealed cavity encasing the components therein.

Abstract: The present invention provides a high heat dissipation plastic package and a method for making the same that provides an inexpensive, thin high heat dissipation plastic package with good bonding precision and minimal bleeding of adhesive resin. A Cu foil resin film is formed by bonding an adhesive resin to a Cu foil and pre-forming, at an essentially central position, a cut-out for a cavity used to mount a semiconductor element. The Cu foil resin film is bonded using the adhesive resin directly to a heat dissipation plate. A conductor wiring pattern is formed on the Cu foil resin film. Furthermore, the heat dissipation plate includes a stopping section used to prevent resin from bleeding onto a cavity when bonding with the adhesive resin of the Cu foil resin film.

Abstract: A semiconductor module includes a fixed type and transformable type coolers and a flat semiconductor package sandwiched between the coolers. A relative positional relationship of the semiconductor package is fixed with the fixed type cooler, but variable with the transformable type cooler. The transformable type cooler includes a transformable member of a metal thin plate covering a coolant chamber. The semiconductor module includes a sandwiching mechanism causing the fixed type cooler to be pressed toward the transformable type cooler. Fastening adjustment screws of the sandwiching mechanism causes a pressing frame to approach a cooler body of the transformable type cooler. Therefore, the semiconductor package is pressed via the fixed type cooler while the transformable member is slightly transformed. This enhances a degree of contact between the semiconductor package and transformable member via an insulating member.

Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

Abstract: The present invention provides a multi-layer substrate structure for reducing layout area, including a first core layer, a second core layer, and a set of coupled transmission line. The first core layer includes a first surface connected to a power supply layer and a second surface corresponding to the first surface. The second core layer includes a third surface connected to a first grounding layer and a fourth surface corresponding to the third surface. The set of coupled transmission lines includes a plurality of first differential signal lines formed on the second surface with a certain line width and a plurality of second differential signal lines formed on the fourth surface with a line width corresponding to the first differential signal lines. The second surface and the fourth surface are connected to a first dielectric layer making the second surface separated from the fourth surface with an appropriated distance.

Abstract: This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.

Abstract: Electrically erasable programmable read only memory (EEPROM) cells and methods of fabricating the same are provided. An EEPROM cell includes an isolation layer formed at a semiconductor substrate to define an active region. A source region, a buried N+ region and a drain region are serially disposed at the active region. A memory gate is disposed to cross-over the buried N+ region. A first channel region is formed between the source region and the buried N+ region. A tunnel region is located between the buried N+ region and the memory gate and self-aligned with the buried N+ region.

Abstract: A light-emitting microelectronic package includes a light-emitting diode (110) having a first region (114) of a first conductivity type, a second region (116) of a second conductivity type, and a light-emitting p-n junction (118) between the first and second regions. The light-emitting diode defines a lower contact surface (120) and a mesa (122) projecting upwardly from the lower contact surface. The first region (114) of a first conductivity type is disposed in the mesa (122) and defines a top surface of the mesa, and the second region (116) of a second conductivity type defines the lower contact surface that substantially surrounds the mesa (122). The mesa includes at least one sidewall (130) extending between the top surface (124) of the mesa and the lower contact surface (120), the at least one sidewall (130) having a roughened surface for optimizing light extraction from the package.

Abstract: A semiconductor device is disclosed that performs fingerprint recognition on the electrostatic-capacity principle. A finger sweeping across a fingerprint recognition area of a semiconductor chip provides positive fingerprint recognition operations with improved reliability. The semiconductor device includes the semiconductor chip having a sensor unit that performs fingerprint recognition, and a substrate having an opening formed in the position corresponding to the sensor unit. The semiconductor chip is flip chip bonded to the substrate such that the sensor unit corresponds to the opening, and except for the formed position of the opening, an under-fill material is provided between the semiconductor chip and the substrate.

Abstract: A magnetoresistive random access memory is provided. The magnetoresistive random access memory includes a first magnetic layer of which the direction of a magnetic vector is fixed, a second magnetic layer which is positioned in parallel with the first magnetic layer and of which the direction of a magnetic vector is reversible, and a non-magnetic layer interposed between the first and second magnetic layers, the second magnetic layer having an aspect ratio of 2 or less, a thickness of 5 nm or less, and a saturation magnetization of 800 emu/cm3 or less. The magnetoresistive random access memory has kink-free, magneto-resistance characteristics, thereby exhibiting high selectivity regardless of process capability.

Abstract: A memory device has a plurality of memory cells, wherein each memory cell has a trench capacitor formed in a semiconductor substrate and an access transistor for it. Each access transistor has a first contact region connected to an internal electrode of the trench capacitor, a second contact region to a bit line and a control electrode region, wherein the control electrode regions of neighboring access transistors are connected by a word line formed in the semiconductor substrate.

Abstract: A semiconductor device includes a substrate with a via hole. An electrode is formed on a surface of the substrate so that a portion of the electrode extends through the via hole. A photosensitive resin is formed over the surface so as to cover an aperture of the via hole.

Abstract: Disclosed herein is a nitride semiconductor light emitting device. The nitride semiconductor light emitting device comprises an n-type nitride semiconductor layer on a substrate, an active layer formed on the n-type nitride semiconductor layer so that a portion of the n-type nitride semiconductor layer is exposed, a p-type nitride semiconductor layer formed on the active layer, a high-concentration dopant area on the p-type nitride semiconductor layer, a counter doping area on the high-concentration dopant areas, an n-side electrode formed on an exposed portion of the n-type nitride semiconductor layer, and a p-side electrode formed on the counter doping area. A satisfactory ohmic contact for the p-side electrode is provided by an ion implantation process and heat treatment.

Abstract: The present invention provides an optical device and a method of manufacture thereof. In one embodiment, the method of manufacturing the optical device may include isolating an end of a first layer from a cladding layer located over a mesa structure that has been formed from a substrate. The end of the first layer may be isolated from the cladding layer by encapsulating the end between second and third layers located adjacent the mesa structure.