Abstract: A semiconductor light-emitting device has a semiconductor layer containing Al between a substrate and an active layer containing nitrogen, wherein Al and oxygen are removed from a growth chamber before growing said active layer and a concentration of oxygen incorporated into said active layer together with Al is set to a level such that said semiconductor light-emitting device can perform a continuous laser oscillation at room temperature.

Abstract: Nanochannel electrophoretic and electrochemical devices having selectively-etched nanolaminates located in the fluid transport channel. The normally flat surfaces of the nanolaminate having exposed conductive (metal) stripes are selectively-etched to form trenches and baffles. The modifications of the prior utilized flat exposed surfaces increase the amount of exposed metal to facilitate electrochemical redox reaction or control the exposure of the metal surfaces to analytes of large size. These etched areas variously increase the sensitivity of electrochemical detection devices to low concentrations of analyte, improve the plug flow characteristic of the channel, and allow additional discrimination of the colloidal particles during cyclic voltammetry.

Abstract: A die attach region for use in an IC package is described. The die attach region employs a number of posts interconnected with a number of support risers to provide a structure that upholds a semiconductor die while facilitating flow of an encapsulant material underneath the die during encapsulation. The posts and risers can be arranged in a number of configurations that each facilitate flow of encapsulant material. This die attach region can be incorporated into a lead-frame structure or a substrate panel for ease and efficiency of manufacture.

Abstract: A nonvolatile semiconductor memory device including a memory cell and a selection transistor, and the memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate formed on the substrate via a second gate insulation film, and a pair of second diffusion layers formed in the substrate positioned on the opposite sides of the selection gate and one of which is electrically connected to one of the pair of first diffusion layers.

Abstract: A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.

Abstract: A method of manufacturing a semiconductor device having a connection terminal and a substrate on which a circuit section and an electrode are stacked in this order, the circuit section having a multilayer interconnect structure, the electrode being conductively connected to the circuit section, and the connection terminal penetrating the substrate and being conductively connected to the electrode. Part of the connection terminal is formed simultaneously with an interconnect in an interconnect layer of the circuit section.

Abstract: In a magnetic random access memory (MRAM) having a transistor and a magnetic tunneling junction (MTJ) layer in a unit cell, the MTJ layer includes a lower magnetic layer, an oxidation preventing layer, a tunneling oxide layer, and an upper magnetic layer, which are sequentially stacked. The tunneling oxide layer may be formed using an atomic layer deposition (ALD) method. At least the oxidation preventing layer may be formed using a method other than the ALD method.

Abstract: Reduced source resistance is realized in a laterally diffused MOS transistor by fabricating the transistor in a P-doped epitaxial layer on an N-doped semiconductor substrate and using a trench contact for ohmically connecting the N-doped source region to the N-doped substrate.

Abstract: An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of the MOSFETs. After die processing, a post-processing test is performed to measure an operating characteristic of the die such as leakage current or switching speed, and an external voltage source is applied and adjusted to control the operating characteristic. The on-die fuses are then cleared to adjust the on-die voltage source to match the externally applied voltage. The operating characteristic may be determined by including a test circuit on the die to exhibit the operating characteristic such as a ring oscillator frequency. This approach to controlling manufacturing-induced device performance variations is well suited to efficient manufacture of small feature-size circuits such as DRAMs.

Abstract: The invention realizes excellent electrical and mechanical connection between electrodes in a packaging structure where a plurality of semiconductor chips having electrodes are connected with each other through the low-melting metallic members. Bump electrodes are formed on a front surface of a first semiconductor chip. Penetrating holes are formed in a second semiconductor chip, and a penetrating electrode having a gap in a center is formed in each of the penetrating holes. Low-melting metallic members are interposed between connecting surfaces of the bump electrodes and the penetrating electrodes, and a part of each of the low-melting metallic members flows in each of the gaps of the penetrating electrodes when dissolved. This prevents short-circuiting between the bump electrodes which is caused by oversupplying the low-melting metallic members between the adjacent bump electrodes.

Abstract: A semiconductor apparatus has a substrate to which is attached a thin semiconductor film including at least one semiconductor device. A first interconnecting line formed on the thin semiconductor film makes electrical contact with the semiconductor device. A second interconnecting line extends from the thin semiconductor film to the substrate, electrically coupling the first interconnecting line to an interconnection pattern on the substrate. At the point where the first and second interconnecting lines meet, one of the two interconnecting lines is widened to provide an increased positioning margin, thereby relaxing the requirement for precise positioning of the thin semiconductor film. The thin semiconductor film may include an array of light-emitting diodes and the substrate may include driving circuitry for driving them.

Abstract: A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.

Abstract: A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode.

Abstract: A magnetic memory includes digit lines, bit lines, and magnetic tunnel junctions (MTJs) that are between the bits lines and the digit lines. The digit lines intersect the bit lines at an oblique angle. The digit lines may intersect the bit lines at an oblique angle of from 15° to 75°.

Abstract: It is an object of the present invention to provide a display device that has a structure of an electrode where a residue of a transparent conductive film is not generated when a weak acid solution is used in etching, which is particularly appropriate for an electrode of a light-emitting element. A display device according to the present invention has an electrode that has a laminated structure of laminated transparent conductive films, and the electrode has a first transparent conductive film as the bottom layer, where no residue is generated when a weak acid solution is used in etching, and a second transparent conductive film as the top layer, which has a work function of 5.0 eV or more.

Abstract: A system and method is disclosed for providing a variable breakdown bipolar transistor. A trench is etched in a substrate between a first area (base/emitter area) and a second area (sinker/collector area). The sinker/collector contact area and a portion of the bottom of the trench adjacent to the sinker/collector area are then heavily doped. The lateral distance between the base/emitter area and the edge of the heavily doped trench determines the breakdown voltage between the emitter and collector and between the base and collector. Heat treatment diffuses the dopant in the bottom of the trench laterally and diffuses the dopant in the sinker/collector area downward until the two areas are joined to form a unified sinker/collector structure.

Abstract: A nonvolatile semiconductor memory device having a small layout area includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The memory cell array includes source line diffusion layers, each of the source line diffusion layers extending along the row direction and connecting in common with the memory cells arranged in the row direction, bitline diffusion layers, element isolation regions which separate each of the bitline diffusion layers, and word gate common connection sections. Each of the memory cells includes a word gate and a select gate. One of the bitline diffusion layers is formed between two word gates adjacent in the column direction Y. Each of the word gate common connection sections is connected with the two word gates above one of the element isolation regions.

Abstract: A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.

Abstract: A GaN compound semiconductor device can be capable of free process design and can have optimum device characteristics. The device can include a group III nitride compound semiconductor laminate structure including an n-type GaN compound semiconductor layer and a p-type GaN compound semiconductor layer. An n electrode can be formed on the n-type GaN compound semiconductor layer, and a p electrode can be formed on the p-type GaN compound semiconductor layer. The n electrode preferably includes an Al layer of 1 to 10 nm, in contact with the n-type GaN compound semiconductor layer, and any metal layer of Rh, Ir, Pt, and Pd formed on the Al layer. The p electrode can be made of a 200 nm or less layer of of Pd, Pt, Rh, Pt/Rh, Pt/Ag, Rh/Ag, Pd/Rh, or Pd/Ag, in contact with the p-type GaN compound semiconductor layer. Both electrodes can make ohmic contact with respective n-type/p-type GaN semiconductors without application of active annealing.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.