Abstract: The present invention includes a method that provides a first wafer; forms a first raised contact from a first plug on the first wafer; provides a second wafer; forms a second raised contact from a second plug on the second wafer; applies an anisotropic conductive adhesive over the first wafer; aligns the second wafer to the first wafer; attaches the second wafer to the anisotropic conductive adhesive to form a continuous and conductive path between the first raised contact and the second raised contact. The present invention also includes a structure that has an anisotropic conductive film, the anisotropic conductive film has a front surface and a rear surface; a first raised contact is located over the front surface, the first raised contact forming part of a first wafer; and a second raised contact located over the rear surface, the second raised contact forming part of a second wafer, where the second raised contact faces the first raised contact.

Abstract: The object of the present invention is to provide a wafer having a structure of enabling an SiC wafer to be put to practical use as a wafer for monitoring a film thickness. For this purpose, an average surface roughness Ra of at least one surface of the SiC wafer is set to be substantially equivalent to a film thickness of a film to be deposited on an Si wafer to be measured. If several types are available to be deposited on an Si wafer to be measured, a minimum film thickness of the film among the several types is determined as an upper limit value, and the average surface roughness Ra of the film thickness measuring SiC wafer is set less than the upper limit value. More concretely, the surface roughness is set to be about 400 times as large as the average surface roughness of a product Si wafer, Ra being preferably set to be 0.08 ?m or less.

Abstract: The semiconductor device comprises logic blocks 12 forming a logic circuit, and interconnection regions 14. A gate interconnection 32a including the gate electrode of a load transistor L1 and the gate electrode of a driver transistor D1, and the source/drain diffused layer 38 of a load transistor L2 are connected to each other by a conductor plug 50b. A gate interconnection 32b including the gate electrode of a load transistor L2 and the gate electrode of a driver transistor D2, and the source/drain diffused layer 35 of the load transistor L1 are connected to each other by a conductor plug 50c. The source/drain diffused layer 37 of a transfer transistor T1 and the source/drain diffused layer 37 of the first driver transistor D1 are made common, and the source/drain diffused layer 40 of the transfer transistor T2 and the source/drain diffused layer 40 of the driver transistor D2 are made common. Accordingly, the area for the memory cells to be formed in can be made very small.

Abstract: A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.

Abstract: The present invention relates to a device for electrostatic discharge protection (ESD).

Abstract: A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.

Abstract: In one embodiment of the invention, a first absorbing layer is on a substrate and/or a second absorbing layer is on a heat-activated adhesive. If the IR source that supplies IR radiation is present on the substrate-side, then the absorption percentage of the substrate is less than the absorption percentage of the first absorbing layer if present and less than the absorption percentage of the second absorbing layer if present. If the IR source that supplies IR radiation is present on the “encapsulation cover”-side, then the absorption percentage of the encapsulation cover is less than the absorption percentage of the first absorbing layer if present and less than an absorption percentage of the second absorbing layer if present. The substrate and the encapsulation cover have a low thermal conductivity.

Abstract: An optically transparent, hermetic coating is locally formed on die and other components already assembled in an existing nonhermetic structure. The local hermetic sealing of an OSA includes providing an OSA having at least one exposed optoelectronic component, and providing a paralene source. The method provides for positioning a mask between the paralene source and the OSA, the mask including an opening aligned with a first region of the OSA. The first region includes at least one of the exposed optoelectronic components. The paralene source is then caused to generate paralene such that a permanent paralene coating is deposited through the opening and on the first region of the OSA. The permanent paralene coating essentially hermetically seals the first region. The permanent paralene coating is chosen to be transparent to the wavelength of light emitted and/or used in the optical sub-assembly.

Abstract: To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first conductors and plural second conductors formed in the first and second regions respectively; a first semiconductor region and a second semiconductor region formed between adjacent first conductors in the first region, the second semiconductor region lying in the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region; a third semiconductor region formed between adjacent second conductors in the second region, the third semiconductor region having the same conductivity type as that of the second semiconductor region and being lower in density than the second semiconductor region; a metal formed on the semiconductor substrate in the second region, the third semiconductor region having a metal contact

Abstract: A surface-mounted LED including a base having heat conductivity, an insulative wiring board fixed to the base and including a conductive pattern and a mounting hole, a light emitting element chip mounted on a mounting area exposed by the mounting hole of the wiring board, and a reflective frame having heat conductivity and fixed to the base and thermally coupled therewith, to surround the light emitting element chip, heat generation from the light emitting element chip being released through both the base and the reflective frame, or either one thereof.

Abstract: A semiconductor memory module includes a wiring board in or on which at least a number of data line runs are conducted in a respective width of k bits and which exhibits a number of memory ranks which in each case have n memory chips, and at least one signal driver/control chip (hub), a k-bit-wide data line run in each case connecting a memory chip from each memory rank to the signal driver/control chip (hub) and four or eight memory ranks in each case being arranged distributed on the top and bottom of the wiring board along the associated data line run in such a manner that, in operation, the load is distributed along the respective data line run.

Abstract: A novel method of manufactring a microchannel plate (“MCP”) is disclosed. The method comprises the steps of ion implantation of a substrate, the subsequent formation of channels paterned on the surface of the substrate and bonding of the subsequent substrate to a handle wafer. The layers are subsequently cleaved and the steps repeated until a MCP structure is achieved. The resulting MCP structure is cost-effective as compared to conventional manufacturing processes and the resulting MCP structure exhibits a funneling effect. The MCP structure may also be used for optical signal amplification for a biochip array.

Abstract: In a charge trapping memory architecture for virtual ground with interconnects (6) that are present parallel to the word lines (2) and STI isolations (1) that are present parallel to the bit lines (4), provision is made of STI isolations (7) that are widened for division into slices. Instead of this, the interconnects present below a bit line may be omitted or two mutually adjacent bit lines (41, 42) may be wired up in such a way that the memory transistors present between them operate only in the dummy mode.

Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Abstract: A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.

Abstract: A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

Abstract: A non-volatile memory array includes memory cells connected in a common source arrangement and formed in columns of isolated well regions so that Fowler-Nordheim tunneling is used for both write and erase operations of the memory cells. The memory arrays can be formed as NOR arrays or NAND arrays. In one embodiment, the memory array of the present invention is formed as a byte alterable EEPROM with parallel access. In another embodiment, an insulated gate bipolar transistor (IGBT) is coupled to the memory cells to increase the cell read current of the memory array. When the memory array incorporates IGBTs on the bitlines, the cell read current becomes independent of the wordline voltages. Thus, the memory array of the present invention can be operated at low voltages. The use of IGBTs in the memory array of the present invention enables formation of embedded non-volatile memories in low-voltage digital integrated circuits.

Abstract: An electronic device including a new oxide layer and a method for manufacturing the same are provided. The electronic device of the present invention includes an oxide layer, which is formed of an oxide containing an element from group IIa, an element from group IIb and an element from group IIIb. For example, it can be applied to a solar cell including a back electrode serving as a first electrode layer, a transparent electrically conductive film serving as a second electrode layer having a light-transmitting property, and a semiconductor layer that is provided between the back electrode and the transparent electrically conductive film and functions as a light-absorption layer, and including an oxide layer provided between the semiconductor layer and the transparent electrically conductive film.

Abstract: Disclosed herein is a ball grid array (BGA) package stack that is not limited by ball arrangement because it utilizes a foldable circuit substrate, which permits interconnection between upper and lower individual BGA packages. The foldable circuit substrate has three portions. By bending the middle second portion, the foldable circuit substrate is folded in two. In the lower BGA package, an IC chip is attached on and electrically connected to a top surface of the first portion, and external connection terminals such as solder balls are formed on a bottom surface of the first portion. The top surface of the first portion is covered with a molding resin to protect the chip, and the third portion is placed on an upper surface of the molding resin. The upper BGA package is constructed in a similar manner to the lower BGA package as described above.

Abstract: A two-wavelength semiconductor laser device includes a first conductive material substrate having thereon first and second regions separated from each other. A first semiconductor laser diode is formed on the first region. A non-active layer is formed on the second region and has the same layers as those of the first semiconductor laser diode. A second semiconductor laser diode is formed on the non-active layer. A lateral conductive region is formed at least between the first and second semiconductor laser diodes.