Abstract: The invention relates to the design, fabrication, and use of semiconductor devices that employ deep-level transitions (i.e., deep-level-to-conduction-band, deep-level-to-valence-band, or deep-level-to-deep-level) to achieve useful results. A principal aspect of the invention involves devices in which electrical transport occurs through a band of deep-level states and just the conduction band (or through a deep-level band and just the valence band), but where significant current does not flow through all three bands. This means that the deep-state is not acting as a nonradiative trap, but rather as an energy band through which transport takes place. Advantageously, the deep-level energy-band may facilitate a radiative transition, acting as either the upper or lower state of an optical transition.

Abstract: A high withstand voltage semiconductor device does not show any significant fall of its withstand voltage if the impurity concentration of the RESURF layer of a low impurity concentration semiconductor region thereof varies from the optimal level and/or influenced by the fixed electric charge.

Abstract: An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

Abstract: A transistor (10) is formed in a semiconductor substrate (12) whose top surface (48) is formed with a pedestal structure (24). A conductive material (40) is disposed along a side surface (28) of the pedestal structure to self-align an edge of a first conduction electrode (45) of the transistor. A dielectric spacer (55) is formed along a side surface (49) of the conductive material to self-align a contact area (56) of the first conduction electrode.

Abstract: An object of the present invention is to provide a large-size light-emitting device from which uniform light emission can be obtained. That is, in the present invention, in a device having an outermost diameter of not smaller than 700 ?m, a distance from an n electrode to a farthest point of a p electrode is selected to be not larger than 500 ?m.

Abstract: A protective film is applied onto a nanostructural feature supported on a sacrificial layer by energy beam assisted deposit of material from a vapor through which the beam passes. A wet etchant is applied to etch away the sacrificial layer beneath the nanostructural feature to leave it suspended as a cantilever or bridge. The film protects the structural feature from damage during etching, and may be removed after the wet etching process is completed.

Abstract: A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.

Abstract: A method for fabrication and a structure of a self-aligned (crosspoint) memory device comprises lines (wires) in a first direction and in a second direction. The wires in the first direction are formed using a hard mask material that is resistant to the pre-selected etch processes used for creation of the lines in both the first and the second direction. Consequently, the hard mask material for the lines in the first direction form part of the memory stack.

Abstract: A non-volatile memory cell is provided. The non-volatile memory at least includes a substrate, a gate, a first source/drain region, a composite dielectric layer and a second source/drain region. A trench is formed in a substrate and a gate is formed inside the trench. The first source/drain region is formed at the bottom of the trench. The composite dielectric layer is formed between the gate and the surface of the trench. The composite dielectric layer includes at least a charge-trapping layer. The second source/drain region is formed in the substrate next to the sides of the gate.

Abstract: An object of this invention is to provide a buried gate-type semiconductor device in which its gate interval is minimized so as to improve channel concentration thereby realizing low ON-resistance, voltage-resistance depression due to convergence of electrical fields in the vicinity of the bottom of the gate is prevented and further prevention of voltage-resistance depression and OFF characteristic are achieved at the same time. A plurality of gate electrodes 106 each having a rectangular section are disposed in its plan section. The interval 106T between the long sides of the gate electrodes 106 is made shorter than the interval 106S between the short sides thereof. Further, a belt-like contact opening 108 is provided between the short sides of the gate electrode 106, so that P+ source region 100 and N+ source region 104 are in contact with a source electrode. Consequently, the interval 106T between the long sides of the gate electrode 106 can be set up regardless of the width of the contact opening 108.

Abstract: The antifuse device comprises an insulating layer positioned in the trench, a conductive member positioned above the insulating layer, at least a portion of the conductive member being positioned within the trench, the conductive member adapted to have at least one programming voltage applied thereto, and at least one doped active region formed in the substrate adjacent the trench. The antifuse further comprises at least one conductive contact coupled to the conductive member, and at least one conductive contact coupled to the doped active region.

Abstract: The optical component includes a substrate made of a resin material, a silicon oxide film formed on a surface of the substrate, and a multilayer light reflection preventing film formed on the silicon oxide film, and having at least one layer of a low-refractive-index material and at least one layer of a high-refractive-index material being alternately formed. The silicon oxide film is thick and/or formed by introducing oxygen during film forming by vacuum deposition so that a preset elasticity is imparted to the silicon oxide film. Other optical component includes a substrate made of a resin material and a plurality of films formed by vacuum deposition, and directions of internal stresses in each adjacent pair of the plurality of films are different from each other or a thickness of an impurity existing on a surface of the substrate is 0.2 nm or less.

Abstract: A semiconductor element includes a semiconductor substrate; a film of electrode material on the substrate at a thickness corresponding to the height of a pair of confronting electrodes standing vertical; a gap in the film of electrode material at a position so that confronting surfaces of the electrodes are formed as having a width corresponding to an interval of the confronting surfaces of the electrodes; and an insulating film in the gap. Then, a pair of confronting electrodes is formed by etching the film of electrode material. An intermediate film is formed on the pair of confronting electrodes; plugs are connected to the pair of confronting electrodes through the intermediate film; and finally wiring is connected to the plugs.

Abstract: Capacitors include an integrated circuit (semiconductor) substrate and an interlayer dielectric disposed on the integrated circuit substrate and including a metal plug therein. A lower electrode is disposed on the interlayer dielectric and contacting the metal plug. The lower electrode includes a cavity therein and a buried layer in the cavity. The buried layer is an oxygen absorbing material. A dielectric layer disposed on the lower electrode and an upper electrode is disposed on the dielectric layer. The lower electrode may be a noble metal layer. The buried layer may fill in the cavity and may not contain oxygen (O2) when initially formed.

Abstract: Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked chips has bonding pads formed on the periphery or edges of its upper surface. At least one insulator is interposed between the stacked chips. The insulator exposes the pads on the underlying chip. The pads of the respective chips are connected to a set of interconnections, which are disposed on the substrate. This configuration of stacked chips enables the overall height of the memory module to be reduced because the insulating film prevents the bonding wires from contacting the substrate of the top chips.

Abstract: A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers.

Abstract: A Heterojunction Bipolar Transistor, HBT, (100) containing a collector layer (104), a base layer (105) and an emitter layer (106) is constructed such that the collector layer (104), the base layer (105) and the emitter layer (106) have different lattice constants of ac, ab and ae respectively, and a value of ab between values of ac and ae (in other words, the values of ac, ab and ae satisfy a relationship of ac>ab>ae or ac<ab<ae). According to the present invention, the HBT having a high reliability can be realized without altering the existing apparatus and steps for producing the HBT extensively.

Abstract: A semiconductor device includes two sense amplifiers provided on a semiconductor substrate. Each of two sense amplifiers is formed of a pair of transistors. Two transistors are separated from each other by an element-isolating insulating portion provided on the semiconductor substrate. Therefore unlike the conventional, two transistors do not share the source region with each other, resulting in a semiconductor device with an improved sensitivity of a sense amplifier.

Abstract: A magnetoresistive effect element (1) has an arrangement in which a pair of ferromagnetic material layers (magnetization fixed layer (5) and magnetization free layer (7)) is opposed to each other through an intermediate layer (6) to obtain a magnetoresistive change by causing a current to flow in the direction perpendicular to the layer surface and in which the ferromagnetic material layers are annealed by anneal including rotating field anneal and the following static field anneal. A magnetic memory device comprises this magnetoresistive effect element (1) and bit lines and word lines sandwiching the magnetoresistive effect element (1) in the thickness direction. When the magnetoresistive effect element (1) and the magnetic memory device are manufactured, the ferromagnetic material layers (5, 7) are annealed by rotating field anneal and the following static field anneal.

Abstract: A transistor device includes a channel of p-type substantially transparent delafossite material. Source and drain contacts are interfaced to the channel. Gate dielectric is between a gate contact and the channel.