Abstract: A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network on a first level, pushing the clock distribution network to a second level, implementing partition clock trees in partitions on the second level, and calculating combined timing of the clock distribution network and the partition clock trees on the second level. Implementing the partition clock trees may include constructing the partition clock trees in the partitions on the second level, calculating trial timing for the partition clock trees, calculating target timing constraints for the partition clock trees based on timing of the clock distribution network and the trial timing for the partition clock trees, and adjusting the timing of one or more of the partition clock trees based on the target constraints.

Abstract: In an example implementation according to aspects of the present disclosure, a method may include determining how many computing devices are in a stackable configuration and selecting an algorithm for charging the computing devices while in the stackable configuration. The method may include, based on the number of computing devices in the stackable configuration, charging the computing devices according to the selected algorithm.

Abstract: In some embodiments, a client device may obtain an external signal. The hardware components of an integrated circuit of the client device may be reconfigured from a first configuration to a second configuration based on information in the external signal such that one or more portions of the integrated circuit that was previously inaccessible is now accessible and an application may access the one or more portions of the integrated circuit. Further, in response to a trigger, the components of the integrated circuit may reconfigure from the second configuration to the first configuration such that the one or more portions of the integrated circuit is inaccessible.

Abstract: The present disclosure discloses a detection circuit and method. The detection circuit comprises: a controller, a battery pack, a main positive switch module, a main negative switch module and at least one detection loop. The controller collects voltages of a positive electrode and a negative electrode of the battery pack and a voltage between external sides of the main positive switch module and the main negative switch module when turning on the main positive or negative switch module and after turning on any detection loop, and obtains resistance values of insulation resistors of the external sides according to resistance values of insulation resistors of internal sides of the main positive and negative switch module, as well as the voltages of the positive electrode and the negative electrode and the voltage between the external sides of the main positive switch module and the main negative switch module, which are collected twice.

Abstract: An industrial truck including a battery and a battery management system connected to the battery and powered by the battery. The battery includes a plurality of battery stacks each having battery cells connected in series with each other, characterized by a control unit adapted to selectively connect one or more of the battery stacks to the battery management system or to disconnect it from the battery management system.

Abstract: Disclosed is a battery management system (BMS) power supply management apparatus and method. The BMS power supply management apparatus includes an optoelectronic element configured to generate a current in response to an optical signal, a conversion element configured to convert the current into a wake-up voltage, and a first switch configured to switch a wake-up signal for a BMS, in response to the wake-up voltage.

Abstract: An energy storage apparatus includes a plurality of energy storage devices connected in series, a voltage detection circuit that detects voltages of the plurality of energy storage devices, and a discharge circuit that discharges the energy storage devices individually, and a BMU having a control unit, in which the control unit discharges only an energy storage device having a highest voltage among the plurality of energy storage devices. Further, charging is stopped when a first duration elapses in a state that a cell voltage of the energy storage device having the highest voltage exceeds a first voltage threshold, or charging is stopped when a second duration elapses in a state that the cell voltage of the energy storage device having the highest voltage exceeds a second voltage threshold.

Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each cluster in the set of dusters is assessed by the machine-learning model to satisfy the one or more design rule constraints, a timing analysis is performed to determine whether each cluster in the set of clusters satisfies the target timing constraints. A clustering solution for the clock net is generated based on the set of clusters in response to determining each cluster satisfies the one or more design rule constraints.

Abstract: An automated system and method of determining power sequencing risks (e.g. power-up, power-down time sequences) for complex computer circuits with multiple independent power supplies. The system operates by logical consideration of the topological arrangement of MOSFETs and other devices in standard netlists. The system inspects the various devices and automatically traces DC circuit paths to DC power rails. The system then evaluates, as a type of logical existence proof, and on a per MOSFET device level, if due to assignment to different DC power levels, various factors, such as forward-biased diodes, floating MOSFET gate, and other risk factors could ever occur. The system generates comprehensive records of such risks and can output an overall analysis of a circuit reporting on both problematic power sequences, as well as circuit design factors that may be sub-optimal from a power sequence perspective.

Abstract: The application relates to direct current, DC, charging cable including two DC conductors configured for transmitting electrical energy between an electrical vehicle and a charging device, at least a signal line having a first signal line end and a second, opposite signal line end and a control device, the first signal line end is connected at a first connection point to one of the DC conductors, and the control device is configured for measuring a voltage difference between the second signal line end and a second connection point of the one of the DC conductors distant to the first connection point for determining a temperature of the DC charging cable.

Abstract: A motherboard having a smart charging function is provided. A connection interface is configured to an electrical device. A first controller is coupled to the switching circuit and communicates with the electrical device via a first transmission path. A second controller is coupled to the switching circuit and communicates with the electrical device via a second transmission path. In a standard charge mode, the first transmission path is turned on and the first controller directs a voltage converter circuit to generate first charge power to the electrical device. In a fast charge mode, the first controller determines whether the electrical device has a specific operating system. Responsive to determining that the electrical device does not have the specific operating system, the second transmission path is turned on and the second controller directs the voltage converter circuit to generate second charge power to the electrical device.

Abstract: A method of manufacturing an integrated circuit includes: generating layout data of the integrated circuit by placing and routing standard cells that define the integrated circuit, the standard cells including a nanosheet; generating timing analysis data by performing a timing analysis of the integrated circuit using the layout data; and regenerating the layout data of the integrated circuit by replacing and rerouting the standard cells that define the integrated circuit based on the timing analysis data and a shape of the nanosheet of the placed standard cells.

Abstract: Data is received that characterizes an integrated circuit and which includes a plurality of Standard Test Interface Language (STIL) codes and at least one file defining physical and/or logical parameters of the integrated circuit. Thereafter, using the received data, a power integrity analysis of the integrated circuit is performed to estimate power induced noise in a double glitch capture mode. Data is then provided that characterizes the performed double glitch capture mode power integrity analysis of the integrated circuit. Related apparatus, systems, techniques and articles are also described.

Abstract: The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and one or more tunable delay buffers, disposed at junctures of the clock network, that operate to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.

Abstract: A battery management method and apparatus is disclosed. The battery management method of a master device includes transmitting, upon a determination of not receiving sensing data of a reference battery cell among a plurality of battery cells included in a first battery module, a request for the sensing data of the reference battery cell to a head slave device of a second battery module, and receiving the sensing data of the reference battery cell from the head slave device of the second battery module, wherein the sensing data of the reference battery cell is transferred through a tail slave device of the first battery module and a tail slave device of the second battery module.

Abstract: A battery cell evaluation apparatus is provided that includes a current source configured to output a current at a frequency, measurement circuitry, and control circuitry. The control circuitry may be configured to electrically connect a cell of a battery to the current source and the measurement circuitry to apply the current across terminals of the cell and receive a measurement of an impedance phase shift of the cell as phase shift data from the measurement circuitry. The control circuitry may also be configured to compare the phase shift data to a protection profile, and trigger a protection device to prevent damage to the battery based on the comparison of the phase shift data to the protection profile.

Abstract: Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of refinement candidates are generated based on the one or more clusters. A scoring function that employs a dynamic weighting scheme is used to determine a refinement quality score for each refinement candidate in the set of candidates and one or more refinement candidates are selected from among the set of refinement candidates based on respective refinement quality scores. A refined clustering solution is generated based on the selected refinement candidates.

Abstract: This invention provides a technique for suppressing deterioration in the value of a power storage system. This invention provides a monitoring system comprising: a detection unit that detects that a detection value related to a power storage system satisfies a condition; a specifying unit that specifies the type of prohibited action executed in the power storage system that satisfies the condition; and a determination unit that, on the basis of the specified type of prohibited action, calculates the life of the power storage system and/or determines the time over which the power storage system can keep operating after the specification.

Abstract: The present application relates to a resistance simulation method for a power device, comprising: establishing an equivalent resistance model of a power device, wherein the connection relationship of N fingers is equivalent to N resistors Rb connected in parallel, input ends of adjacent resistors Rb are connected by means of a resistor Ra, output ends of adjacent resistors Rb are connected by means of a resistor Rc, R a = 1 N ? R 0 , R c = 1 N ? R 1 , and Rb=RDEV*N+RS+RD, wherein R0 and R1 are respectively resistances of a source metal strip and a drain metal strip, Rs is a metal resistor of a first intermediate layer connecting one source region to the source metal strip, RD is a metal resistor of a second intermediate layer connecting one drain region to the drain metal strip, and RDEV is the channel resistance of the power device; and calculating the resistance of the equivalent resistance model as the resistance of the power device.

Abstract: A fixing device and a fixing method for a clock tree are provided. The fixing method for the clock tree includes: performing a clock signal path tracking operation on a netlist of a circuit according to timing constraint information to obtain a clock tree circuitry structure; identifying a convergency status of the clock tree circuitry structure to find out at least one clock convergence point, and setting one of a plurality of clock signals on the clock convergence point as a selected clock signal; performing a fix point identification operation on the clock tree circuitry structure based on the selected clock signal to obtain a plurality of candidate fix points; and calculating a plurality weighting values of the candidate fix points, obtaining a plurality of selected fixed points according to the weighting values.