Patents Examined by Mohammed Alam
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Patent number: 11461529Abstract: Routing a circuit path includes selecting pixels on the circuit path based at least on penalty values associated with the pixels. Pixels on a rejected circuit path are penalized by increasing their penalty values. Re-routing a rejected circuit path allows for pixels on previously rejected paths to be considered when rerouting the rejected circuit path, rather than being eliminated outright.Type: GrantFiled: April 20, 2021Date of Patent: October 4, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Matus Lipka, Kenneth Reneris
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Patent number: 11461523Abstract: A method for performing glitch power analysis of a circuit, comprising receiving no-timing waveform simulation data for the circuit, the waveform simulation data including a first signal, and identifying a delayed stimulus injection point (DSIP) for the first signal. The method further comprises determining a total delay for the first signal and performing waveform replay simulation including injecting the first signal at the DSIP at a time based on the total delay for the first signal.Type: GrantFiled: February 5, 2021Date of Patent: October 4, 2022Assignee: Synopsys, Inc.Inventors: Chia-Tung Chen, Che-Hua Shih, Shih-Ting Liu, Chia-Chih Yen, Chun Chan, Gung-Yu Pan, Yi-An Chen
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Patent number: 11453299Abstract: The invention relates to systems and methods for charging a vehicle. A vehicle and charging station can be designed such that an electric or hybrid vehicle can operate in a fashion similar to a conventional vehicle by being opportunity charged throughout a known route.Type: GrantFiled: November 24, 2020Date of Patent: September 27, 2022Assignee: Proterra Operating Company, Inc.Inventors: Donald Morris, Dale Hill, John Horth, Reuben Sarkar, Teresa J. Abbott, William Joseph Lord Reeves, Ryan Thomas Wiens
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Patent number: 11449657Abstract: Area and routing overhead issues of traditional anamux incorporation in a semiconductor device are overcome by placing a functional anamux block on top of an I/O pad. In some embodiments, multiple anamux blocks can be stacked either vertically or placed on neighboring I/O pads for horizontal stacking. Embodiments provide the anamux blocks as the same width as the I/O pads and the width is optimized to minimize padring height. In some embodiments, a power/ground I/O (PGE) bond pad architecture is enabled by the incorporation of both I/O pad and anamux blocks in the same region, providing two bonding regions, which can further reduce chip area. Some embodiments also permit routing of signals through the anamux block to neighboring blocks and the I/O channels.Type: GrantFiled: December 16, 2020Date of Patent: September 20, 2022Assignee: NXP USA, Inc.Inventors: Wenzhong Zhang, Ajay Kumar Sharma, Rishi Bhooshan
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Patent number: 11436397Abstract: A computer-implemented method and an electronic device for detecting, in an electrical circuit with electrical components (Mg) subject to variations (?) of their model parameters (xj), those components (Mg*) the model parameter variations (?) of which have the strongest influence on a performance (yn) of the circuit, comprising: providing a topology (Q) of the circuit and the model parameters (xj) of all components (Mg) therein; determining, therefrom, topological patterns (Pk) of interconnected components (Mg); generating variation samples (vn), each comprising a different set of candidate variations (x?j) of the model parameters (xj); calculating, for each variation sample (vn), the circuit's performance (yn) and a deviation from a standard performance and forming a deviation vector (yD) therefrom; and using the variation samples (vn), the deviation vector (yD) and the topological patterns (Pk) in a regression model for detecting the most influential components (Mg*).Type: GrantFiled: September 11, 2019Date of Patent: September 6, 2022Assignee: TECHNISCHE UNIVERSITÄT WIENInventors: Hiwa Mahmoudi, Horst Zimmermann
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Patent number: 11431038Abstract: Systems and methods for a flexible, head-mounted display is provided. The head-mounted display system may comprise a base member and one or more arm members that are coupled to the base member. Each of the arm members are coupled to the base member via a hinge that allows the arm members to move with respect to one another. Interior walls of the arm members and base member may define one or more chambers. One or more first batteries are positioned within a chamber in the first arm member and one or more second batteries are positioned within a chamber in the second arm member. One or more wired connections coupled to the batteries extend through the arm member(s) and hinges, and into one or more chambers in the base member, where the one or more wired connections are coupled to a battery monitor.Type: GrantFiled: June 18, 2020Date of Patent: August 30, 2022Assignee: RealWear, Inc.Inventors: Sanjay Subir Jhawar, Nima Lahijani Shams
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Patent number: 11415898Abstract: First and second metrology data are used to train a machine-learning model to predict metrology data for a metrology target based on metrology data for a device area. The first metrology data are for a plurality of instances of a device area on semiconductor die fabricated using a fabrication process. The second metrology data are for a plurality of instances of a metrology target that contains structures distinct from structures in the device area. Using the trained machine-learning model, fourth metrology data are predicted for the metrology target based on third metrology data for an instance of the device area. Using a recipe for the metrology target, one or more parameters of the metrology target are determined based on the fourth metrology data. The fabrication process is monitored and controlled based at least in part on the one or more parameters.Type: GrantFiled: December 20, 2019Date of Patent: August 16, 2022Assignee: KLA CorporationInventor: Stilian Pandev
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Patent number: 11409941Abstract: A method of designing a semiconductor chip includes: acquiring first data including information about arrangement of a plurality of cells on the semiconductor chip; acquiring second data including information about routing between the plurality of cells and power and signal lines; and outputting a verification result by detecting an error of arrangement of the plurality of cells based on matching of the first data and the second data.Type: GrantFiled: February 9, 2021Date of Patent: August 9, 2022Assignee: Samsung Electronics Co., Ltd.Inventor: Sunghoon Lee
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Patent number: 11392744Abstract: Systems and methods that may be implemented to automatically sense and verify proper mated orientation of a removable BGA package relative to a mating pad array (e.g., of a BGA socket) prior to supplying power to the BGA package. A removable BGA package may be provided with first and second symmetric pins so as to present different respective circuit states on opposing sides of a center point of its BGA package pin array, such that proper orientation of the BGA package occurs only when a designated one of the first and second symmetric pins is mated with a designated pad of the mating pad array. A programmable integrated circuit may in turn sense the circuit state presented at the designated pad to verify proper orientation of the mated BGA package based on the sensed circuit state presented at the designated pad, and may take one or more designated actions based on whether or not proper orientation of the mated BGA package is verified.Type: GrantFiled: October 9, 2020Date of Patent: July 19, 2022Assignee: Dell Products L.P.Inventors: Geroncio O. Tan, Lip Vui Kan, Merle Wood, III, Wei Cheng Yu
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Patent number: 11392749Abstract: A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.Type: GrantFiled: November 18, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, KuoPei Lu, Lester Chang, Ze-Ming Wu
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Patent number: 11392741Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.Type: GrantFiled: April 16, 2020Date of Patent: July 19, 2022Assignee: Arm LimitedInventor: Paul Christopher de Dood
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Patent number: 11386251Abstract: A logic simulation verification system designates a change timing designation unit configured to designate a reference signal and a change timing and calculate a first time for which there is a possibility that a first signal to be assigned to a variable described in a library, a circuit description, and a test bench is changed in accordance with the reference signal. The system calculates a second time for which there is a possibility that a second signal assigned a variable described in the library, the circuit description, and the test bench will be checked in accordance the reference signal and then determines whether different circuits for which first signals are the same have first times that match. The system also determines whether a first time and a second time match with each other when a first signal of one circuit and a second signal of another circuit are the same.Type: GrantFiled: March 2, 2021Date of Patent: July 12, 2022Assignee: KIOXIA CORPORATIONInventor: Toshiyuki Sakamoto
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Patent number: 11386250Abstract: A method of detecting a timing violation between a first sequential element and a second sequential element in a circuit design being emulated in a hardware emulation system includes, in part, determining a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element, reconfiguring a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers, setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship, reprogramming the first and second clocks in accordance with the delay, and detecting a timing violation if a change in an output of the first flip-flop is not stored in the second flip-flop within the delay.Type: GrantFiled: January 26, 2021Date of Patent: July 12, 2022Assignee: Synopsys, Inc.Inventors: Dmitry Korchemny, Nathaniel Azuelos, Boris Gommershtadt, Alexander Shot
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Patent number: 11381093Abstract: Disclosed herein are battery management systems and methods for activating battery override logic for a battery management system to provide a power path to a battery pack. A method of activating battery override logic for a battery management system may comprise detecting a predetermined key toggle sequence performed in a predetermined amount of time or detecting an override message received from a CAN bus. The method may further comprise determining if the last override turn-on sequence was requested more than a predetermined amount of time ago, confirming that the override is configured for the contactor, and turning on the contactor to provide a power path to the battery pack for a limited predetermined amount of time. An exemplary predetermined toggle sequence may comprise on-off-on-off-on performed within 10 seconds. An exemplary override message from the CAN bus may be initiated by a user having a key, code, or access card.Type: GrantFiled: November 22, 2019Date of Patent: July 5, 2022Assignee: Green Cubes Technology, LLCInventor: Anthony H. Cooper
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Patent number: 11366950Abstract: Methods and systems herein can efficiently interconnect processors through a custom grid (a data mesh) utilizing upper metal layer routing in a semiconductor die design to minimize latency. A computer-implemented method of routing interconnects on a semiconductor die includes receiving a set of non-default routes and associated routing rules; identifying a set of critical signals for feedthrough on the set of non-default routes; generating a connectivity matrix including a set of resulting routes, the resulting routes routing the set of critical signals through the set of non-default routes; generating a timing analysis of the connectivity matrix based on a set of latency requirements; responsive to determining that the timing analysis is not compliant with the latency requirements, generating a set of routing constraints; and updating the associated routing rules to include the set of routing constraints.Type: GrantFiled: January 14, 2021Date of Patent: June 21, 2022Assignee: CADENCE DESIGN SYSTEMS, INC.Inventors: Mitchell G. Poplack, Tarik Hanai Omar, TheHung Luu, Zaid Khan, Jerome Albert
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Patent number: 11361140Abstract: Automated routing of signal nets for interposer designs. Signal nets are defined by their endpoints (bumps). The nets and their corresponding bumps are assigned to bump groups, based on the relative locations of the bumps and also based on length-matching constraints for the nets. Some of the bump groups may be “clones,” where the routing for one bump group may also be applied to its clone. In order for two bump groups to be clones, the bumps in the two bump groups must have a same relative position (i.e., same bump pattern), and the nets in the two bump groups must be subject to the same length-matching constraint. The routing through the interposer for one of the clones is determined, and that routing is then replicated for the other clones.Type: GrantFiled: November 10, 2020Date of Patent: June 14, 2022Assignee: Synopsys, Inc.Inventors: Jitendra Kumar Gupta, Ksenia Roze, Xun Liu, Paul Chang, Lan Luo
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Patent number: 11354471Abstract: Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.Type: GrantFiled: May 28, 2020Date of Patent: June 7, 2022Assignee: CELERA INC.Inventors: Calum MacRae, Karen Mason, John Mason, Richard Philpott
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Patent number: 11354483Abstract: Improved parasitic analysis of a design of an electrical circuit (e.g. a PCB coupled to an IC package) can use a first parasitic analysis to identify a first set of pins having excessive parasitic values (“hotspots” in the design) and then identify a second set of pins that do not have excessive parasitic values. The pins in the second set can be clustered (e.g. using a grid of cells) to reduce a model size for calculations in a second parasitic analysis, and the pins in the first set can be analyzed in the second parasitic analysis either individually or in clusters of similar pins with excessive parasitic values.Type: GrantFiled: January 6, 2021Date of Patent: June 7, 2022Assignee: ANSYS, INC.Inventor: Prakash Vennam
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Patent number: 11349316Abstract: A circuit for controlling a battery includes a switch. The switch includes a source, a gate, and a drain. The drain of the switch is configured to be connected to a positive terminal of the battery. The circuit also includes a first diode. The first diode includes an anode and a cathode. The anode of the first diode is connected to the source of the switch. The cathode of the first diode is connected to the drain of the switch and is configured to be connected to the positive terminal of the battery. The circuit also includes a second diode. The second diode includes an anode and a cathode. The anode of the second diode is configured to be connected to a negative terminal of the battery. The cathode of the second diode is connected to the source of the switch and to the anode of the first diode.Type: GrantFiled: April 20, 2020Date of Patent: May 31, 2022Assignee: THE BOEING COMPANYInventor: Robert J. Atmur
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Patent number: 11347916Abstract: Clock skew may be increased along a critical path of a systolic array. Pipelined registers may be added between a bus that provides input data signals to a systolic array and between a bus that receives output data signals from the systolic array. Skew circuitry for the pipelined registers may be implemented to delay a clock signal to the pipelined registries to allow a clock skew accumulated along a critical path of the systolic array to exceed a single clock cycle.Type: GrantFiled: June 28, 2019Date of Patent: May 31, 2022Assignee: Amazon Technologies, Inc.Inventors: Nishith Desai, Thomas A. Volpe