Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises an initial buffer tree for a net in the IC design. A maximum cost constraint for rebuffering the net is determined based on the initial buffer tree. A partial rebuffering solution is generated for net and a cost associated with the partial rebuffering solution is determined. Based on determining the cost of the partial rebuffering solution satisfies the maximum cost constraint, the partial rebuffering solution is saved in a set of partial rebuffering solutions for the net. A set of candidate rebuffering solutions for the net is generated based on the set of partial rebuffering solutions, and a rebuffering solution for the net is selected from the set of candidate rebuffering solutions. The database is updated to replace the initial buffer tree in the IC design with the rebuffering solution selected for the net.

Abstract: A method for building a simulation program with integrated circuit emphasis (SPICE) circuit model of an optical coupler is provided. The method includes: providing a plurality of electrical parameters of the SPICE circuit model of the optical coupler circuit for a plurality of temperature values, and building the SPICE circuit model of the optical coupler at each of the temperature values according to the electrical parameters of the optical coupler for each of the temperature values, so as to form a plurality of temperature-independent SPICE circuit models of the optical coupler; forming a plurality of temperature-voltage conversion switch circuit elements by utilizing control of a voltage source and temperature characteristics of an impedance; and connecting the temperature-voltage conversion switch circuit elements to the temperature-independent SPICE circuit models of the optical coupler, respectively, so as to build a temperature characterized SPICE circuit model of the optical coupler.

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

Abstract: Aspects of the present disclosure address systems and methods for clock tree synthesis (CTS). A first iteration of CTS is performed to generate an intermediate clock tree for an integrated circuit (IC) design that includes one or more macros. Target pin insertion delays (PIDs) for the one or more macros are computed based on the intermediate clock tree using a linear program. A second iteration of CTS is performed using the target PIDs for the one or more macros to generate an optimized clock tree for the IC design.

Abstract: Techniques for computer aided design and engineering of integrated circuits can use group identifiers of correlated signals and time delay values when using vectorless dynamic voltage drop (DVD) simulations and when using other types of simulations or analyses of a circuit design. A method in one embodiment can include the operations of: receiving a design representing an electrical circuit that includes a plurality of pins, the plurality of pins including one or more input nodes or one or more output nodes in the electrical circuit; identifying, in the design, one or more groups of pins that are correlated such that, within each identified group, all of the pins in the identified groups switch between voltage states in a correlated way; assigning, for each pin in each identified group, an identifier for the identified group and a time delay value based on the pin's delay from an initial point in the identified group's logic chain to the pin.

Abstract: A power storage device 20 comprises: a plurality of power storage elements C1-C6 that are connected in series; energy transfer circuits 40 provided respectively to the plurality of power storage elements C1-C6; a common bus 50 to which the energy transfer circuits 40 of the plurality of power storage elements C1-C6 are commonly connected; and a control device 70. Each energy transfer circuit 40 includes one or a plurality of switching transformers Tr, each switching transformer having a first winding 41A that is connected to the power storage elements C1-C6 and a secondary winding 41B that is connected to the common bus 50. The control device 70 uses the switching transformers Tr of the energy transfer circuits 40 to transfer energy between the power storage elements via the common bus 50, thereby equalizing the voltages of the power storage elements C1-C6. The common bus 50 is in an electrically floating state.

Abstract: This disclosure provides an apparatus for a portable thermal power station and related methods. The power station includes a burner, a reservoir, an output power plug, and a thermoelectric generator. The burner produces combustible heat across a surface. The reservoir stores a cooling fluid. The output power plug electrically connects to an external device. The thermoelectric generator receives heat energy, converts the heat energy to electrical energy, outputs the converted electrical energy to the external device, and disperses excess heat energy to the reservoir.

Abstract: A battery management apparatus includes: a first transceiver configured to receive a first infrared (IR) signal output from a neighbor battery management apparatus and process the first IR signal; a controller configured to extract information from the processed first IR signal; and a second transceiver configured to output a second IR signal based on the extracted information.

Abstract: A hybrid battery system is provided for extending the shelf-life of rechargeable batteries. The hybrid battery system may contain sets of non-rechargeable and rechargeable batteries respectively. As the rechargeable batteries are discharged (e.g., from self-discharge), the hybrid battery system may utilize the non-rechargeable batteries to maintain the rechargeable batteries at a preferred state of charge. A preferred state of charge may be selected to extend the shelf-life of the rechargeable batteries. Alternatively, a signal may change the preferred state of charge to prepare the rechargeable batteries for use or for other reasons. The hybrid battery system may contain modular components, thereby allowing for easy replacement of defective or otherwise unsuitable non-rechargeable batteries, rechargeable batteries, or supporting electronics.

Abstract: An information processing apparatus includes a conversion unit configured to convert circuit configuration data representing a configuration of an electric circuit including an input terminal group and an output terminal group into circuit calculation data including an equation group that generates an output signal group corresponding to an argument group given to a variable group and an input signal group given to the input terminal group, wherein the argument group includes a constant representing a characteristic of a circuit element that forms the electric circuit.

Abstract: A battery management system (103) for a battery (100) comprising a plurality of battery cells (101, 102) connected in parallel with each other. The battery management system comprises an electronic circuit (104) for connection across at least one of the plurality of battery cells. The electronic circuit comprises a charge storage device (105) and a switching device (106). The switching device switches the circuit between a first state in which charge is discharged from the at least one battery cell and directed to the charge storage device and a second state in which charge is discharged from the charge storage device and directed to the at least one battery cell. The switching device is arranged to repeatedly switch the circuit between the first state and the second state to cause the at least one battery cell to undergo pulsed charging and discharging to and from the charge storage device.

Abstract: Methods, systems, devices and apparatuses for a wireless charger for charging an electronic device within a vehicle. The wireless charger includes a first sensor. The first sensor is configured to measure or detect a temperature of the electronic device. The wireless charger includes a thermoelectric device. The thermoelectric device is configured to adjust the temperature of the electronic device or a surface of the charging pad. The wireless charger includes a processor coupled to the first sensor and the thermoelectric device. The processor is configured to determine that the temperature of the electronic device exceeds a first threshold temperature and control the thermoelectric device to increase or decrease the temperature of the electronic device or the surface of the charging pad.

Abstract: A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.

Abstract: A method, system and computer program product, the method comprising: obtaining circuit information of a portion of a circuit design, the circuit information specifying a plurality of electronic components and a plurality of nets connecting pins of components from the plurality of components, the portion of the circuit design thereby associated with a plurality of nodes comprising the pins and connection points, and one or more ground nodes connected to a ground net; obtaining a set of logical prediction rules and algorithms applicable to circuit designs; applying to the portion of the circuit design one or more applicable rules or algorithms from the set of logical prediction rules and algorithms, to obtain: a predicted potential of one or more nodes, and one or more electrical values for one or more electronic component; and outputting the predicted potential or the electrical values predicted for the electronic components.

Abstract: Methods for iteratively optimizing a two-dimensioned tiled area such as a lithographic mask include determining a halo area around each tile in the tiled area. An extended tile is made of a tile and a halo area. Each extended tile in the tiled area is iterated until a criterion is satisfied or a maximum number of iterations is met. Optimizing the extended tile produces a pattern for the tile such that at a perimeter of the tile, the pattern matches adjacent patterns that are calculated at perimeters of adjacent tiles.

Abstract: Battery packs according to embodiments of the present technology may include a first battery cell including a lithium-containing material. The first battery cell may be configured to operate in a voltage window extending to or above about 4 V. The battery packs may include a second battery cell electrically coupled in parallel with the first battery cell. The second battery cell may be configured to operate in a voltage window maintained at or below about 4.0 V. The battery packs may also include a controller configured to receive a measured terminal voltage from the first battery cell. The controller may be configured to determine whether to disconnect the second battery cell from the first battery cell based on the measured terminal voltage of the first battery cell.

Abstract: A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

Abstract: Carry out an initial wire-length-driven placement for an integrated circuit design embodied in an unplaced netlist, using a computerized placer, to obtain a data structure representing initial placements of logic gates. Identify at least one timing-critical source-sink path between at least one pair of source-sink endpoints in the data structure representing the initial placements. Create a new pseudo two-pin net for each pair of the at least one pair of source-sink endpoints to create an updated netlist. Carry out a revised wire-length-driven placement on the updated netlist to obtain a data structure representing revised placements.

Abstract: A charging cradle includes: a cradle housing having a base portion, and a socket portion configured to interchangeably receive (i) a mobile device, (ii) a battery pack for the mobile device, and (iii) the mobile device in combination with the battery pack; the socket portion including: a shared base surface having disposed thereon a set of shared charging contacts; a first set of guide surfaces extending from the shared base surface and defining a first socket configured to receive the mobile device and, in the absence of the battery pack, to engage the shared charging contacts with a first set of contacts on the mobile device; and a second set of guide surfaces extending from the shared base surface and defining a second socket configured to receive the battery pack and engage the shared charging contacts with a second set of contacts on the battery pack.