Abstract: Provided is a technique capable of improving test efficiency of semiconductor devices. A test apparatus includes a probe card having a plurality of measurement sites that contact with a plurality of semiconductor devices formed on a semiconductor wafer; a control unit configured to generate map information, probe-card form information, and contact-position information, the map information including position information and peculiar information of the semiconductor devices on the semiconductor wafer, the probe-card form information including arrangement information of the measurement sites, the contact-position information indicating a contact position that is a range of the semiconductor device tested at one time by the probe card based on constrained-condition information of limiting contact with the probe card; and a position control unit configured to control a relative position between the probe card and the semiconductor wafer based on the contact-position information.

Abstract: Example devices and methods for compensating for monitoring a surge protection device are provided. In some embodiments, a device is configured to couple to a surge protection device. The device comprises a processor that is capable of sending a DC current signal. A serial data interface is electrically connected to the processor and includes at least one shift register. The device also comprises a multiplexer coupled to the serial data interface. The serial data interface is operable to direct the DC current through the multiplexer. The device also comprises an analog to digital converter (optionally embedded within the processor) that is operable to output a digital signal corresponding to a voltage induced by the DC current signal. Returned DC signals represent surge protection device's health and a multitude of other surge module information.

Abstract: Evaluation board (EVB) assemblies or stacks utilized in tuning electronic modules are disclosed, as are methods for tuning such modules. In embodiments, the module testing assembly includes an EVB and an EVB baseplate. The EVB includes, in turn, an EVB through-port extending from a first EVB side to a second, opposing EVB side; and a module mount region on the first EVB side and extending about a periphery of the EVB through-port. The module mount region is shaped and sized to accommodate installation of a sample electronic module provided in a partially-completed, pre-encapsulated state fabricated in accordance with a separate thermal path electronic module design. A baseplate through-port combines with the EVB through-port to form a tuning access tunnel providing physical access to circuit components of the sample electronic module through the EVB baseplate from the second EVB side when the sample electronic module is installed on the module mount region.

Abstract: A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.

Abstract: The semiconductor inspecting method includes following steps. First, a first position of a probe needle from above is defined by adopting a vision system of a semiconductor inspecting system. Then, a first relative vertical movement between the probe needle and the pad is made by adopting a driving system of the semiconductor inspecting system. Thereafter, a minimum change in position of the probe needle corresponding to the first position is recognized by adopting the vision system of the semiconductor inspecting system. Next, the first relative vertical movement is stopped by adopting the driving system of the semiconductor inspecting system.

Abstract: A current transformer having a body having an upper half and a lower half hingedly connected to the upper half, a pair of ferrite cores located within one of the upper half and the lower half of the body, the pair of ferrite cores defining a gap formed between each ferrite core of the pair of ferrite cores, and a sensor located within the gap formed between each ferrite core of the pair of ferrite cores.

Abstract: A system for testing circuits of an integrated circuit semiconductor wafer includes a tester system for generating signals for input to the circuits and for processing output signals from the circuits for testing the wafer and a test stack coupled to the tester system. The test stack includes a wafer probe for contacting a first surface of the wafer and for probing individual circuits of the circuits of the wafer, a wafer thermal interposer (TI) layer operable to contact a second surface of the wafer and operable to selectively heat areas of the wafer, and a cold plate disposed under the wafer TI layer and operable to cool the wafer. The system further includes a thermal controller for selectively heating and maintaining temperatures of the areas of the wafer by controlling cooling of the cold plate and by controlling selective heating of the wafer TI layer.

Abstract: Aspects of the invention include a wafer test device with a conformal laminate and rigid probes extending from the laminate to form an electrical connection with a microcircuit under test. The wafer test device also includes a spring plate on a side of the laminate that is opposite a side from which the rigid probes extend. The spring plate includes a conformal inner frame and a rigid outer frame. The laminate is attached to the inner frame of the spring plate.

Abstract: The probe assembly operates with a circuit board test apparatus and includes a main test probe and a secondary test probes. The probe assembly is capable of moving in X, Y and Z directions relative to a circuit board being tested (UUT). The two test probes are movable linearly relative to each other and rotatable together so as to accurately locate the two probes on selected pins on the UUT, for receiving signals from the selected pins, The received signals are transmitted to a display apparatus.

Abstract: A testing system for test sockets is presented having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A top stiffener is attached to the lower surface of the DUT PCB and is locked in place by engagement members of a locking mechanism, that is operated by an actuating mechanism, that includes a rack and pinion arrangement that converts rotational movement of the pinions to lateral movement of the racks thereby locking the stiffener connected to the DUT PCB to the socket plate so as to facilitate testing. The upper surface of the DUT PCB has an infinite top plane that is uninterrupted and can be of any size and shape. The system is also modular and can be formed of any number of modules depending on the pin count density required.

Abstract: A method for processing a substrate by using fluid flowing through a particle detector is provided. The particle detector is utilized to detect nano-particles contained in fluid. The particle detector includes a substrate and a pair of sensing electrodes disposed on the substrate. The substrate includes nano-pores, wherein the pore size of the nano-pores is greater than the particle size of the nano-particles, allowing the nano-particles contained in the fluid passing through the nano-pores. The pair of sensing electrodes are positioned adjacent to at least one of the nano-pores.

Abstract: A probe apparatus and a wafer inspection method are provided. The probe apparatus includes a chuck configured to support a wafer, a track surrounding the chuck, a tester disposed on the track and having a probe, and a processing unit in communication with the tester and configured to move the tester circumferentially around the wafer such that the probe is moved from a first portion on the wafer to a second portion on the wafer.

Abstract: An inspection apparatus includes: a probe card having a probe to be in contact with an object to be inspected; an upper module having a mounting portion on which the object to be inspected is mounted; a movement mechanism that is configured to support the upper module to be liftable and lowerable and that is able to move the upper module in a horizontal direction; and a lifting and lowering mechanism that is provided under the movement mechanism and that is able to push up the upper module toward the probe card, wherein an axis passing through a point of action of a pushing force when the lifting and lowering mechanism pushes up the upper module and an axis passing through a point of action of a load received by the probe card are arranged at positions to be common.

Abstract: The present disclosure relates to voltage sensing mechanisms. One example embodiment includes a voltage-measurement device. The voltage-measurement device includes a housing. The voltage-measurement device also includes an extendible gripper configured to be removably attached to a wire under test. Additionally, the voltage-measurement device includes at least one power supply. Further, the voltage-measurement device includes a power management chip electrically coupled to the at least one power supply and configured to manage a range of input voltages from the at least one power supply. The power management chip comprises a synchronous boost voltage regulator. Additionally, the voltage-management device has a microprocessor electrically coupled to the power management chip and the extendible gripper. The microprocessor is configured to receive electrical power from the power management chip.

Abstract: A method of characterizing a field-effect transistor, including: a step of application, to the transistor gate, of a single voltage ramp; and a step of interpretation both of gate capacitance variations and of drain current variations of the transistor.

Abstract: An example polarity inverter includes multiple contactors, each of which includes switches that are controllable to configure a current path. Each of the multiple contactors includes contacts, which are interleaved such that first contacts to receive voltage having a first polarity alternate with second contacts to receive voltage having a second polarity, where the first polarity and the second polarity are different. The polarity inverter also includes a first conductive plate to connect electrically to each of the first contacts, and a second conductive plate to connect electrically to each of the second contacts. The first conductive plate and the second conductive plate are in parallel. A dielectric material is between the first conductive plate and the second conductive plate.

Abstract: The invention relates to a distance-measuring device for determining a distance between a reflection body in a conducting structure and a coupling region for electromagnetic waves, which region is provided on an end section of the conducting structure, said measuring device comprising a transmitting and receiving device, and a conduction junction (1) provided on the coupling region, for coupling the transmitting and receiving device to the conducting structure containing a medium, in order to couple an electromagnetic wave into the conducting structure, and to decouple the electromagnetic wave, reflected on the reflection body, from the conducting structure. Said measuring device also comprises an evaluation device for determining the distance between the coupling region and the reflection body from the complex reflection coefficient between the coupled electromagnetic wave and the decoupled electromagnetic wave. The invention also relates to the corresponding method.

Abstract: A display device including a substrate having a display area and a non-display area outside the display area, a plurality of pixels disposed on the substrate in the display area, an external circuit bonded on the substrate in the non-display area, a first signal line disposed on the substrate in the non-display area and surrounding at least a portion of the display area, the first signal line being electrically connected to the external circuit, and a second signal line disposed in the non-display area and surrounding at least a portion of the first signal line, the second signal line being electrically connected to the external circuits.

Abstract: Disclosed is a probe card for testing a wafer. The probe card includes a substrate and a block including an insulation portion and a conducting portion disposed on the insulation portion. Here, the insulation portion includes a via and a probe pin which comes into contact with an object to be tested. The conducting portion includes a contact point electrically connected to the substrate and a conducting pattern passing through the via and electrically connecting the contact point to the probe pin. A pitch between a plurality of such probe pins is smaller than a pitch between a plurality of such contact points. The block includes a plurality of unit blocks. The plurality of unit blocks each include the insulation portion and the conducting portion, and at least parts of the insulation portions of the unit blocks are arranged while being spaced apart from each other.

Abstract: A Fast Faraday Cup includes a group of electrodes including a grounded electrode having a through hole and a collector electrode configured with a blind hole that functions a collector hole. The electrodes are configured to allow a beam (e.g., a non-relativistic beam) to fall onto the grounded electrode so that the through hole cuts a beamlet that flies into the collector hole and facilitates measurement of the longitudinal distribution of particle charge density in the beam. The diameters, depths, spacing and alignment of the collector hole and the through hole are controllable to enable the Fast Faraday day cup to operate with a fast response time (e.g., fine time resolution) and capture secondary particles.