Abstract: In a method and apparatus for scalable deduplication, a data set is partitioned into multiple logical partitions, where each partition can be deduplicated independently. Each data block of the data set is assigned to exactly one partition, so that any two or more data blocks that are duplicates of each are always be assigned to the same logical partition. A hash algorithm generates a fingerprint of each data block in the volume, and the fingerprints are subsequently used to detect possible duplicate data blocks as part of deduplication. In addition, the fingerprints are used to ensure that duplicate data blocks are sent to the same logical partition, prior to deduplication. A portion of the fingerprint of each data block is used as a partition identifier to determine the partition to which the data block should be assigned. Once blocks are assigned to partitions, deduplication can be done on partitions independently.

Abstract: An address lock register managing address exclusive control is made to retain not only an address but also a request type, an access destination, and a cache block. Upon receiving a new request, firstly, the address lock register is referred to judge whether an exclusive condition is satisfied, that is, whether an address match, CPU match, LINE match or SX-WAY match is present, and whether the address lock is busy in accordance with the output of an AND circuit. Further, the configuration is such that the address lock register is referred to confirm that the addresses are identical to each other, and, additionally, the response source is validated to be identical to a lock flag and the new request causing the lock is validated to be consistent with the response request upon receiving a response request so that the lock is not released unless a correct response is made.

Abstract: A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.

Abstract: Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.

Abstract: A translation lookaside buffer may include control functionality coupled to a first storage and a second storage. The first storage includes a first plurality of entries for storing address translations corresponding to a plurality of page sizes. The second storage includes a second plurality of entries for storing address translations corresponding to the plurality of page sizes. In response to receiving a first address translation associated with a first page size, the control functionality may allocate the first plurality of entries to store address translations corresponding to the first page size. In addition, in response to receiving a request including an address that matches an address translation stored within the first storage, the control functionality may copy a matching address translation from the first storage to the second storage.

Abstract: Information objects and system firmware for a processor in a partitionable computing system are disclosed. One object comprises information corresponding to components of the computer system. The information comprises entries defining an address and a size for registers normally accessible to other partitions. The registers are capable of defining an address area such that in use the processor is arranged to permit other partitions to access at least one address area defined by the at least one register and to deny other partitions access to address areas other than the at least one accessible address area.

Abstract: A method and system using a storage controller for transferring data between a storage device and a host system is provided. The storage controller includes, a power save module that is enabled in a power save mode after a receive logic in the storage controller has processed all frames and during the power save mode at least a clock is turned off to save power while a clock for operating the receive logic is kept on to process any unsolicited frames that may be received by the receive logic. The storage controller operates in a single frame mode during the power save mode to process any unsolicited frames. Setting a bit in a configuration register for a processor enables the power save mode. The power save mode is enabled after a memory controller is in a self-refresh mode.

Abstract: Apparatus and method to receive new requests for write transactions; compare rank, bank and page of new requests to those already stored and assemble chains of write commands directed to the same rank, bank and page; select and transmit write commands from one chain at a time until each chain is done; and select a next chain of write commands to transmit, while creating and using a write page closing hint to determine when a change between pages of a given rank and bank should bring about the preemptive closing of a page to minimize incidents of incurring lengthy page miss delays.

Abstract: Data in data runs are stored in a non-volatile memory array in adaptive metablocks that are configured according to the locations of data boundaries. A serial flash buffer is used to store some data, while other data are directly stored in non-volatile memory. Data may be stored with alignment to data boundaries during updating of the data to improve efficiency of subsequent updates.

Abstract: Techniques for pushing data to multiple processors in a clean state.

Abstract: A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track completion of invalidations. The central coherency controller reads snoop tags to identify sharing caches having a copy of a requested cache line. The central coherency controller sends an ordering message to the requesting filter pipe. The ordering message has an invalidate count indicating the number of sharing caches. Each sharing cache receives an invalidation message from the central coherency controller, invalidates its copy of the cache line, and sends an invalidation acknowledgement message to the requesting filter pipe. The requesting filter pipe decrements the invalidate count until all sharing caches have acknowledged invalidation.

Abstract: A method and circuit to implement a match against range rule functionality. A first rule entry and a second rule entry are stored. The first rule entry includes at least two consecutive identical bits. The first rule entry represents a numerical range. A first field of a binary key is compared with the first rule entry to determine whether any of the bits of the first field are not identical. A logical result of the comparison between the first field and the first rule entry is inverted to generate a first comparison result. A second field of the binary key is compared with a second rule entry to generate a second comparison result. The first comparison result is then logically ANDed with the second comparison result to determine whether the binary key falls within the numerical range represented by the first rule entry and matches the second rule entry.

Abstract: Provided are a method, system, and article of manufacture, wherein a request to write data to a storage medium is received. The data requested to be written to the storage medium is stored in a cache. A writing of the data is initiated to the storage medium. A periodic determination is made as to whether the stored data in the cache is the same as the data written to the storage medium.

Abstract: A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.

Abstract: In a data processing system utilizing multiple page sizes for virtual memory paging, a system, method, and article of manufacture for managing page replacement. In one embodiment, the page replacement method begins with a page frame allocation request, such as may be generated following a page fault. A page replacement procedure is invoked to select one or more pages to be replaced by the requested page(s). In a preferred embodiment, the page replacement includes a step of selecting, in accordance with a page type allocation of at least one of the multiple page sizes, a page size to be utilized for page replacement for the page frame allocation request.

Abstract: A method for applying software controlled caching and ordered thread optimizations in network applications includes collecting statistics for program variables, selecting program variable candidates for ordered synchronization and/or software controlled cache optimization, performing a safety check to ensure candidates can be properly optimized, and generating code for selected optimization candidates.

Abstract: The storage system includes a disk controller for receiving write commands from a computer, and a plurality of disk devices in which data is written in accordance with the control of the disk controller. The size of the first block which constitutes the data unit handled in the execution of the input/output processing of the data in accordance with the write command by the disk controller is different from the size of the second block which constitutes the data unit handled in the execution of the input/output processing of data by the plurality of disk devices. The disk controller issues an instruction for the writing of data to the disk devices using a third block unit of a size corresponding to a common multiple of the size of the first block and the size of the second block.

Abstract: During sampling intervals, pairs of swap scores are assigned to respective pairs of storage devices of a storage system, each swap score pair indicating an amount of system performance improvement for a swap of logical volumes between source and target storage devices of the pair of storage devices. The swap scores are summed over all the intervals. A subset of the storage devices are then selected for a full optimization process based on the summed swap scores, where the full optimization process exhaustively looks for some number of best swaps among the storage devices to improve system performance. By choosing the size of the subset of storage devices, the processing burden required to perform the analysis will be in line with the processing capacity of the processing platform on which the analysis is performed, while achieving system performance improvement commensurate with a worst-case process in which every storage device in the system is analyzed for candidate swaps.

Abstract: A mapping tool for hierarchical storage mapping may include a storage hierarchy representation interface, a command interface and remapping software. The storage hierarchy representation interface may be configured to provide a user with representations of a source storage hierarchy and target storage devices, where the source storage hierarchy may include a source storage device with one or more contained storage devices. The command interface may allow the user to request a hierarchical mapping of the source storage device to one or more target storage devices. The remapping software may be configured to create a mapping of the source storage device and the contained storage devices to storage within the target storage devices.

Abstract: Transactions are granted concurrent access to a data item through the use of an optimistic concurrency algorithm. Each transaction gets its own instance of the data item, such as in a cache or in an entity bean, such that it is not necessary to lock the data. The instances can come from the data or from other instances. When a transaction updates the data item, the optimistic concurrency algorithm ensures that the other instances are notified that the data item has been changed and that it is necessary to read a new instance, from the database or from an update instance.