Abstract: A multi-processor system includes a requesting node that provides a first request for data to a home node. The requesting node being operative to provide a second request for the data to at least one predicted node in parallel with first request. The requesting node receives at least one coherent copy of the data from at least one of the home node and the at least one predicted node.

Abstract: A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.

Abstract: A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read only memory (EPROM) with a faster CPU. A method and system has been devised which uses interleaving techniques and memory sub-sections. A memory interlace controller interfaces a faster CPU to several sub-sections of slower memory. The memory interlace controller interlaces the access of the slower memory and thus optimizing the CPU system speed.

Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

Abstract: Techniques are provided for resolving a collision between two copy services. A policy associated with a new copy service request is retrieved. Characteristics of an existing copy service request are determined. The effects of the new copy service request are determined. A resolution for the collision is identified based on the policy, the determined characteristics, and the determined effects.

Abstract: A technique translates a hybrid virtual volume (vvol) having a file system that contains intermingled virtual and physical volume block numbers (vbns) into a “pure” stream of virtual vbns (vvbns). The stream of vvbns is illustratively embodied as an output file system data stream of a vvol image that is transferred by a source storage system (“source”) to a destination storage system (“destination”) in accordance with image transfer operations, such as volume copying and synchronous or asynchronous mirroring, provided by a volume replication facility. The blocks that are sent as part of the image transfer are selected from a container file of the hybrid vvol on the source. In particular, the invention is directed to a technique for translating physical vbns (pvbns) of a source aggregate on the source to pure vvbns of the output file system data stream that can be used on a destination aggregate of the destination, where embedded pvbns in the source hybrid vvol image are not valid.

Abstract: An apparatus and method provides the capability of mirroring storage from a primary system to a mirrored system in a way that uses parallelism in the mirrored system to maximize the efficiency of writing data to the mirrored storage for operations that do not conflict while serializing operations that do conflict. The mirroring of the present invention is “logical mirroring”, which does not require identical disk drives, and which supports mirroring between geographically remote locations to protect against catastrophic site failure. Parallelism is achieved in the mirrored system by dividing the virtual address space into multiple ranges, and by assigning a group of tasks to each range. When an operation is received on the mirrored system, the virtual address range that the operation affects is determined, and the operation is then delegated to the task group that corresponds to the affected virtual address range. By dividing the virtual address space into ranges, tasks in different ranges (i.e.

Abstract: A method and system for determining the memory utilization of a heap are provided. With the method and system, object allocations and optionally, possible memory freeing events are used to initiate a mark-and-count operation. The mark-and-count operation marks the live objects and maintains a running count of their memory bytes allocated to the live objects, referred to as a live count. The execution of the mark-and-count operation may be dependent upon various criteria including thresholds, functions of the live count, peak live counts, number of memory bytes allocated since a previous mark-and-count operation was performed, and the like. In addition to the live count, a peak live count may be obtained and updated as new peak live counts are identified. When the peak live count is updated, additional information may be obtained via a heap dump, arcflow tree, or the like.

Abstract: The storage regions under command of a storage controller can be simply enabled and disabled to access to by automatically registering connected host computers. Such system can be achieved by taking a step of acquiring N_Port_Name information included in a login frame from the host computers, and a step of displaying a table of access right of host computers to a logical unit under command of storage controller. A security table for the storage controller can be generated by supervisor's setting the access enable/disable flag information.

Abstract: An object of the present invention is to provide a memory controller that can perform a series of data write operations so as to complete the data writing at high speed. A memory controller includes means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to a different group, and means for assigning adjacent host addresses to different physical blocks belonging to the same virtual block. Thus, when a host computer issues a request to access the plurality of successive host addresses, the physical blocks to be accessed are different physical blocks. Since the physical blocks to be accessed can therefore operate independently, a series of operations can be performed in parallel.

Abstract: A shift register is provided to monitor the difference between the read and write pulses to an elasticity buffer. The shift register essentially eliminates the need for any math functions in the elasticity buffer management logic. The shift register is as wide as the elasticity buffer is deep. In other words, for every word in the elasticity buffer, the shift register has a corresponding bit. Each time a word is written into the elasticity buffer without a simultaneous corresponding read, a value of “1” is shifted from a first end into the shift register, indicating that a space has been taken in the elasticity buffer. For every word read out of the elasticity buffer without a simultaneous corresponding write, a value of “0” (zero) is shifted from a second end of the shift register, indicating that one more space is available.

Abstract: A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other threads to reclaim its queue node immediately (in the absence of preemption), or mark its queue node to allow reclamation by a successor thread.

Abstract: A method to maintain information by assigning one or more storage attributes to each of a plurality of logical volumes. The method writes a first portion of a dataset to a first logical volume. The method assigns one or more storage attributes to that first logical volume. When the logical end of volume for the first logical volume is approaching, Applicants' method mounts a second logical volume, and continues writing the dataset to that second logical volume. The method assigns the same one or more storage attributes to the second logical volume.

Abstract: A method of optimizing performance of a memory subsystem in a computer system. This method including the step of informing the computer system of what type of memory module loading is present in the memory subsystem. The method also includes operating the memory subsystem at a first frequency that is at a chosen ratio to a second frequency at which a frontside bus (FSB) operates. Further, the method includes optimizing the performance of the memory subsystem by changing the ratio.

Abstract: A method for securing stored data for use in a computer is disclosed. The method includes the steps of providing a data to be stored in data storage device, addressing a data-storing request to the data storage device, wherein the data-storing request includes a first storing position data, proceeding an operation on the first storing position data to obtain a second storing position data, and writing the data into the data storage device according to the second storing position data. The operation for changing the first storing position data to the second storing position data is performed by a driver corresponding to the data storage device.

Abstract: A processor includes a memory unit in which instructions having their constituent bytes stored in ascending address order alternate with instructions having their constituent bytes stored in descending address order. A single address pointer is used to read one instruction by reading up, and another instruction by reading down. The amount of address information needed for program execution is thereby reduced, as one address pointer suffices for two instructions. The address pointer may be provided by a branch instruction that also indicates whether to read up or down. An up-counter and a down-counter may be provided as address counters, enabling the two instructions to be read and executed concurrently. Four address counters may be provided, enabling a branch instruction to designate the execution of from one to four consecutive instructions.

Abstract: When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.

Abstract: A content addressable memory comprises a CAM control logic unit and plural cells connected in a chain. Each cell comprises a memory block coupled to a common address bus, a comparator coupled to a common data bus and to the data interface of the memory block. A switch couples the data interface of the memory block with the data bus, and a logic block including a Match flip-flop. The memory is operable in a Search phase and an Access phase. In the Search phase, a sequence of words on the common data bus is serially matched with the contents of a sequence of addresses in the memory blocks. In the Access phase, the cells matched in the Search phase are made serially available for access via common address and data buses.

Abstract: Disclosed is a device and method such that data of size S is stored in a memory of size K, a two-dimensional matrix with R rows and C columns, and interleaving indexes I are generated according to a predetermined interleaving rule to randomly output the data from the memory. If a first index I is greater than data size S, a second index is generated and output prior to outputting invalid data stored in the memory at the location of the first index.

Abstract: A cache includes an error circuit for detecting errors in the replacement data. If an error is detected, the cache may update the replacement data to eliminate the error. For example, a predetermined, fixed value may be used for the update of the replacement data. Each of the cache entries corresponding to the replacement data may be represented in the fixed value. In one embodiment, the error circuit may detect errors in the replacement data using only the replacement data (e.g. no parity or ECC information may be used). In this manner, errors may be detected even in the presence of multiple bit errors which may not be detectable using parity/ECC checking.