Patents Examined by Ngoc Dinh
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Patent number: 7325113Abstract: Memory protection apparatus to protect memory area to realize high interruption response and prohibit from access to the memory area that is previously designated. The memory area data registers 132 (1) to (m), respectively, retain data which designate the accessible memory area in the processing corresponding to interruption of the group number corresponding to it. Selection circuit 133 selects any of the memory area data registers 132 (1) to (m) according to the group number retained by the group number register 131, and outputs data that designates selected memory area retained by the memory area data registers 132. Address bus watching part 106 watches generation of illegal memory access of the processor according to the data designating the memory area output by the selection circuit 133.Type: GrantFiled: March 23, 2005Date of Patent: January 29, 2008Assignee: NEC Electronics CorporationInventor: Hideki Matsuyama
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Patent number: 7325115Abstract: An operating system copies data from memory pages into a paging file on disk, in order to free up space in the memory. A mechanism is disclosed that causes the data to be encrypted as it is copied into the paging file, thereby protecting the paged data from unauthorized (or otherwise undesired) observation. The data that is stored in the paging file is encrypted with a session key, that is generated shortly after the machine on which the paging file exists is started. The session key, which is used both for encryption and decryption of the paging file data, is stored in volatile memory, so that the key is not persisted across boots of the machine. Since the key is not persisted across boots, old paging file data that was stored prior to the most recent boot cannot be recovered in clear text, thereby protecting the data from observation.Type: GrantFiled: November 25, 2003Date of Patent: January 29, 2008Assignee: Microsoft CorporationInventors: Benjamin A. Leis, David B. Cross, Duncan G. Bryce, Jianrong Gu, Rajeev Y. Nagar, Scott A. Field
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Patent number: 7321962Abstract: A method for transferring data of a hybrid virtual volume of a computer data storage system from a source to a destination is disclosed. The method first translates intermingled virtual and physical volume block numbers of the hybrid virtual volume into a data stream having only virtual volume block numbers. The method then sends the data stream to a destination computer.Type: GrantFiled: February 7, 2007Date of Patent: January 22, 2008Assignee: Network Appliance, Inc.Inventors: Robert L. Fair, Ashish Prakash, Eric Hamilton, John K. Edwards, Robert M. English
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Patent number: 7318137Abstract: The current invention is a blocking device that provides read and write protection for computer long-term storage devices, such as hard drives. The blocking device is placed between a host computer and the storage device. The blocking device intercepts communications between the host and the storage device and examines commands from the host to the storage device. Certain commands, such as commands that may modify the storage device, may be discarded. The current invention enables multiple host computers to communicate to the blocking device. The current invention selectively blocks only specified host computers.Type: GrantFiled: January 27, 2004Date of Patent: January 8, 2008Inventors: Steven Bress, Mark Joseph Menz
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Patent number: 7315916Abstract: In a memory array having a minimum unit of erase of a block, a scratch pad block is used to store data that is later written to another block. The data may be written to the scratch pad block with a low degree of parallelism and later written to another location with a high degree of parallelism so that it is stored with high density. Data may be temporarily stored in the scratch pad block until it can be more efficiently stored elsewhere. This may be when some other data is received. Unrelated data may be stored in the same page of a scratch pad block.Type: GrantFiled: December 16, 2004Date of Patent: January 1, 2008Assignee: SanDisk CorporationInventors: Alan David Bennett, Sergey Anatolievich Gorobets
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Patent number: 7308529Abstract: A technique for processing a request requiring that a first volume of removable storage media be mounted on a storage device is disclosed. It is determined whether the storage device is available. In the event it is determined that the storage device is not available because it currently has mounted on it a second volume of removable storage media associated with a data mover, it is determined whether the data mover should be asked to permit the second volume to be removed from the storage device so that the first volume can be mounted thereon. In the event it is determined that the data mover should be asked to permit the second volume to be removed from the storage device so that the first volume can be mounted thereon, the data mover is prompted to provide an indication that the second volume may be dismounted from the storage device.Type: GrantFiled: June 30, 2004Date of Patent: December 11, 2007Assignee: EMC CorporationInventor: Ravindranath S. Desai
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Patent number: 7308535Abstract: A buffer output manager facilitates automatic self-triggering output of buffer contents. At least one processes writes control data to at least one buffer, the control data being such that a buffer output trigger address can be determined therefrom. For each buffer to which control data is written, a buffer output manager determines the trigger address of that buffer. At least one process writes data to at least one buffer, including to the trigger address thereof. For each buffer to which data is written to the trigger address, the buffer output manager automatically outputs the contents of that buffer, responsive to the writing of the data to the trigger address.Type: GrantFiled: August 25, 2004Date of Patent: December 11, 2007Assignee: QLogic, CorporationInventor: Dave Olson
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Patent number: 7302535Abstract: For a storage system having plural control units to which plural disk devices are connected, in the method for creating replication in a volume of the disk devices connected to different control units, when receiving update I/O of a replication source during an initial copy for replication, the reflection of update to the replication destination is performed on an extension of the same I/O. When a pair is divided after the completion of copying, the update position is retained on the differential bitmap disposed in the individual control units, and the differential bitmap is merged to one of the control units at a time of resynchronization to perform copy processing.Type: GrantFiled: June 30, 2004Date of Patent: November 27, 2007Assignee: Hitachi, Ltd.Inventors: Ai Satoyama, Noboru Morishita, Yasutomo Yamamoto
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Patent number: 7302543Abstract: An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.Type: GrantFiled: June 16, 2004Date of Patent: November 27, 2007Assignee: NEC Laboratories America, Inc.Inventors: Haris Lekatsas, Joerg Henkel, Srimat Chakradhar, Venkata Jakkula
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Patent number: 7281083Abstract: According to embodiments of the present invention, a network processor includes a content addressable memory (CAM) unit having CAM arranged in banks and sharable among microengines. In one embodiment, a mask having a value is used to select/enable one group of CAM banks and to deselect/disable another group of CAM banks. A tag may be looked up in the selected/enabled CAM banks based on the mask value. Upon a “miss,” the CAM banks provide the least recently used (LRU) entry. A LRU entry reelection tree may reelect the LRU entry from among all the CAM banks.Type: GrantFiled: June 30, 2004Date of Patent: October 9, 2007Assignee: Intel CorporationInventor: Tomasz B. Madajczak
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Patent number: 7281105Abstract: In a selective logical-volume swapping process, a subset of storage devices in a storage system are selected that represent good candidates for swaps that will improve system performance. Workload statistics are utilized from a number of sample intervals in a relatively long analysis interval. The workload statistics are aggregated over intermediate intervals of each analysis interval to yield a set of aggregated statistics much smaller than the set of workload statistics. Based on the aggregated statistics, a service processor searches for swaps of logical volumes, ranks the swaps according to expected system performance improvement, and selects source and target storage devices of the higher-ranked swaps. The service processor can then perform a full optimization analysis for this subset of storage devices utilizing the workload statistics from all the sample intervals.Type: GrantFiled: March 23, 2005Date of Patent: October 9, 2007Assignee: EMC CorporationInventors: Hui Wang, Ron Arnan, Tao Kai Lam
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Patent number: 7281106Abstract: In an optimization dispatch process for a storage system, M storage devices are identified for an optimization analysis process to be executed to identify logical volume swaps for improving system performance. The M storage devices are identified by merging candidate storage devices obtained from separate identification algorithms employing distinct identification criteria. The analysis process is dispatched for execution based on the M storage devices until (i) a successful completion upon which a best swap has been identified, or (ii) a resource-based stop condition such as an execution time limit. M is adjusted for a subsequent iteration such that over time a desired rate of successful completions is achieved. For example, M is increased by a first amount upon a successful completion and decreased by a second amount upon the stop condition.Type: GrantFiled: March 23, 2005Date of Patent: October 9, 2007Assignee: EMC CorporationInventors: Ron Arnan, Hui Wang, Tao Kai Lam
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Patent number: 7281098Abstract: Provided is a computer system capable of maintaining consistency of data stored in logical volumes. The computer system includes: a storage system including a disk controller which controls data read/write in a disk drive; and a host computer which transmits a request to the storage system, wherein the disk controller has a control unit and a storage unit, the disk drive has logical volumes which are data storing areas, the host computer sends a request directed to the logical volume and attribute information of the logical volume, the control unit wherein: executes the received request; the control unit stores, in the storage unit, the received attribute information in association with the logical volume; and decides to execute a following request which is made by the host computer to the logical volume in a case where the request meets the attribute information corresponding to the logical volume and is stored in the storage unit.Type: GrantFiled: June 7, 2005Date of Patent: October 9, 2007Assignee: Hitachi, Ltd.Inventors: Yuri Hiraiwa, Nobuhiro Maki, Kenta Ninose, Katsuhisa Miyata, Takashige Iwamura
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Patent number: 7277985Abstract: The present invention takes advantage of unused storage space within the ESS cells to provide for the efficient and cost effective storage of downloadable content. Specifically, the system of the present invention generally includes a download grid manager that communicates with the ESS cells. Content to be replicated to the ESS cells, and characteristics corresponding thereto, are received on the download grid manager from a content owner (or the like). Based on the characteristics, a storage policy, and storage information previously received from the ESS cells, the download grid manager will replicate the downloadable content to unused storage space within the ESS cells.Type: GrantFiled: July 13, 2004Date of Patent: October 2, 2007Assignee: International Business Machines CorporationInventors: Irwin Boutboul, Moon J. Kim, Dikran Meliksetian, Robert G. Oesterlin, Anthony Ravinsky, Jr.
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Patent number: 7275127Abstract: There is disclosed a multi-application transponder circuit for a contactless electronic identification and/or access system including, in particular, a non-volatile memory (18) having a segmented programmable memory space for receiving data relating to a plurality of distinct applications, this memory space including (i) a first memory zone (A) segmented into several memory words each dedicated to storage of data relating to a determined application from among said plurality of distinct applications, (ii) a second memory zone (B), called a shared zone, segmented into several memory words each able to be allocated to storage of data relating to any application from among said plurality of distinct applications, and (iii) a third memory zone (C) containing indications relating to the allocation of memory words of said second memory zone, at least, and for determining which memory word or words of said second memory zone are allocated to storage of data relating to a given application from among said plurality oType: GrantFiled: July 12, 2004Date of Patent: September 25, 2007Assignee: EM Microelectronic-Marin SAInventor: Riad Kanan
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Patent number: 7266671Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.Type: GrantFiled: December 6, 2004Date of Patent: September 4, 2007Assignee: Broadcom CorporationInventors: Mark Taunton, Sophie Wilson, Timothy Martin Dobson
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Patent number: 7263587Abstract: A unified memory controller (UMC) is disclosed. The UMC may be used in a digital television (DTV) receiver. The UMC allows the DTV receiver to use a unified memory. The UMC accepts memory requests from various clients, and determines which requests should receive priority access to the unified memory.Type: GrantFiled: June 25, 2004Date of Patent: August 28, 2007Assignee: Zoran CorporationInventors: Gerard Yeh, Ravi Manyam, Viet Nguyen
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Patent number: 7254669Abstract: A method for storing customer data at a non-volatile storage (NVS) at a storage server. A track buffer is maintained for identifying first and second sets of segments that are allocated in the NVS. A flag in the track buffer identifies which of the first and second sets of segments to use for storing customer data for which a write request has been made. The customer data is stored in the NVS in successive commit processes. Following a power loss in the storage server, the NVS uses the track buffer information to identify which of the first and second sets of segments was involved in the current commit process to allow the current commit process to be completed.Type: GrantFiled: January 29, 2004Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Kevin J. Ash, Michael T. Benhase
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Patent number: 7243205Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.Type: GrantFiled: November 13, 2003Date of Patent: July 10, 2007Assignee: Intel CorporationInventors: Chris B. Freeman, Pete D. Vogt, Kuljit S. Bains, Robert M. Ellis, John B. Halbert, Michael W. Williams
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Patent number: 7240157Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.Type: GrantFiled: September 26, 2001Date of Patent: July 3, 2007Assignee: ATI Technologies, Inc.Inventors: Michael Frank, Santiago Fernandez-Gomez, Robert W. Laker, Aki Niimura