Abstract: This invention provides a method and apparatus for controlling the current drawn in a multi-bank memory device, for example, in a multi-bank memory system. The above and other features and advantages of the invention are achieved by a method and apparatus which controls access to a memory device to prevent an over-current condition. Each memory request is processed for each memory bank as an arbitrated event. A request is coordinated with the local memory controller circuitry controlling access to the memory bank. The memory bank is checked for its availability. The total current demand of the memory device is determined. If the memory bank request would not create an over-current condition and the memory bank is available, then the memory bank request is acknowledged and the memory request is carried out. Also provided is a method of fabricating such a memory device and also a method of operating such a memory device to access a selected memory bank.

Abstract: A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a multiple memory pages. The memory management unit includes a security check receiving a physical address within a selected memory page, and security attributes of the selected memory page. The security check unit uses the physical address to access one or more security attribute data structures located in the memory to obtain an additional security attribute of the selected memory page. The security check unit generates a fault signal dependent upon the security attributes of selected memory page and the additional security attribute of the selected memory page. The security attributes of the selected memory page may include a user/supervisor (U/S) bit and a read/write (R/W) bit as defined by the ×86 processor architecture. The one or more security attribute data structures may include a security attribute table directory and one or more security attribute tables.

Abstract: In a method of controlling stores to and reads from a cache, if a read request is in a read queue, then a read is performed. If no read is in the read queue and if a store request is in a store queue and if an early read predict signal is not asserted, then a store is performed. If no read is in the read queue and if a store request is in the store queue and if the early read predict signal is asserted, if a read is detected a read is then performed. Otherwise, if the early read predict is subsequently de-asserted, then a store is performed.

Abstract: Methods and apparatus for dynamically allocating space within virtual memory at run-time while substantially minimizing an associated path length are disclosed. According to one aspect of the present invention, a method for allocating virtual storage associated with a computer system includes creating a scratchpad, allocating a unit of storage space at a current location within the scratchpad, and writing a set of information into the unit of storage space such that the set of information is substantially not tracked. The scratchpad supports allocation of storage space therein, and includes a first pointer that identifies a current location within the scratchpad. Finally, the method includes moving the first pointer in the scratchpad to identify a second location within the scratchpad. The first pointer moves in the first linear space in substantially only a top-to-bottom direction.

Abstract: If one of the HDDs of a disk array fails, a disk array controller regenerates the data stored in the failed HDD and stores the regenerated data in another HDD used in place of the failed HDD. To be more specific, the disk array controller checks each of the stripes of the disk areas of the disk array and determines whether each stripe is used by a file system. This determination is based on a disk resource management table. Then, the disk array controller regenerates data by use of RAID technology only for a stripe that has been determined as being used by the file system.

Abstract: A CRC value cache architecture and methods of operation of same to reduce overhead processing associated with managing a CRC value cache memory. The invention first provides for transferring from system memory to CRC value cache memory all CRC values for all sub-blocks of a data block in response to access to a first CRC value for a first sub-block. This reduces overhead processing to arbitrate for control of the system memory for each CRC value for each sub-block of a block. The invention additionally provides that a separate cache table is maintained corresponding to each device within the storage controller that requests CRC values. Each of the multiple cache entry tables is therefore shorter and more rapidly searched as compared to prior techniques thereby further reducing overhead processing to manage the cached CRC values.

Abstract: In a multiprocessor data processing system including: a memory, first and second shared caches, a system bus coupling the memory and the shared caches, first, second, third and fourth processors having, respectively, first, second, third and fourth private caches with the first and second private caches being coupled to the first shared cache, and the third and fourth private caches being coupled to the second shared cache, gateword hogging is prevented by providing a gate control flag in each processor. Priority is established for a processor to next acquire ownership of the gate control word by: broadcasting a “set gate control flag” command to all processors such that setting the gate control flags establishes delays during which ownership of the gate control word will not be requested by another processor for predetermined periods established in each processor.

Abstract: A copying method, disk storage system, and storage medium for copying data from one logical disk to another logical disk, making possible immediate access, in response to a copy command. Copying from a first logical disk to a second logical disk is performed for each area in a copy range, and when there is an access to either logical disk, copying is interrupted. When performing update access of an uncopied area in the first logical disk, the area is copied from the first logical disk to the second logical disk, and then the uncopied area is updated. When performing reference access of an uncopied area in the second logical disk, the corresponding area in the first logical disk is referenced. When performing update access of an uncopied area in the second logical disk, that area in the second logical disk is updated, and copying is prohibited.

Abstract: Techniques for implementation of Java heaps are disclosed. The techniques can be implemented in a Java virtual machine operating in a Java computing environment. A Java heap potion comprising two or more designated portions is disclosed. Each of the designated heap portions can be designated to store only a particular Java logical component (e.g., Java objects, Java class representation, native components, etc.) A designated heap portion can be implemented as a memory pool. In other words, two or more designated heap portions can collectively represent a memory pool designated for a particular Java logical component. The memory pools allow for dynamic management of the designated heap portions. As a result, the performance of the virtual machines, especially those operating with relatively limited resources is improved.

Abstract: A system 100 including a central processing unit 101 operates in response to a set of instructions for processing information. A port 134 provides access to selected circuitry forming a part of the system by an external device. A set of non-volatile programmable security elements 136 selectively enable and disable the operation of the interface to provide a private environment for processing the information.

Abstract: The present invention coordinates the execution of commands, received in response to a continuous system clock, with the receipt of data in response to a burst clock. Command capture logic receives command information in response to the system clock. A storage element is responsive to the command capture logic for storing certain command information such as write commands. A two stage pipeline receives the command information from the storage element in response to the burst clock and outputs the command information in response to the system clock. Methods of operating the apparatus are also disclosed.

Abstract: An N-way set associative data cache system comprises a cache controller adapted to receive a request for data and instructions. The cache controller includes a cache buffer register for storing the requests for a line of information in the form of a page tag address and line address. The line address is stored in the buffer register as a pointer into a directory associated with each of the N-ways for determining where the line being accessed resides. If the page tag address matches one of the page entry addresses in one of the directories, there is a hit, but if not, the line of data must be fetched by a cache fill request. The line of data is retrieved from an L2 cache or main memory and written into the line of one of the ways at the line address being accessed. A novel LRU ordering tree or look-up table is provided for determining concurrently the one line in the number of N-lines in the cache to be replaced with the new line of data in the event of a miss.

Abstract: An apparatus and method for preserving a region code for an optical disk drive in an internal flash memory contained in a microcomputer. This region code preserving method receives a region code to be written, copies a part of the firmware for the optical disk drive stored in memory means to an external memory, and writes the received region code in the memory means separately from the firmware by the execution of the copied firmware.

Abstract: A data reader is arranged to read data comprising user data 30 and non-user data 32, 34 written across at least two channels of a data-holding medium 10, said data being arranged into a plurality of data items 26 each containing user data and non-user data, with said non-user data holding information relating to said user data, said data reader having a read head 12 for reading a respective said channel of said data-holding medium 10 to generate a data signal 14 comprising said data items, and processing circuitry 250 arranged to receive and process said data signals to identify a set CCPset1 of said data items written at the same time onto different said channels. Identifying a set of data items written at the same time gives rise to the possibility of correcting header information for the data items in a set.

Abstract: In a computer system with caching, memory transactions can retrieve and store groups of lines. Coherency states are maintained for groups of lines, and for individual lines. A single coherency transaction, and a single address transaction, can then result in the transfer of multiple lines of data, reducing overall latency. Even though lines may be transferred as a group, the lines can subsequently be treated separately. This avoids many of the problems caused by long lines, such as increased cache-to-cache copy activity. In one alternative, when a cache memory requests a group of lines, and when the group of lines is partially owned by another cache memory, then the requesting cache receives fewer than all the lines in the requested group.

Abstract: Featured is a method for reducing overhead associated with system input output (I/O) operations in a computer system having a plurality of processors and a physical memory accessed and used by the plurality of processors. The physical memory being accessed can be a global physical memory such as that used with SMP types of architectures or distributed physical memory such as that used with CCNUMA types of architectures. Such a method includes creating a pinned virtual memory range database in which is stored virtual memory address information corresponding to pinned physical memory for each applications program being run on the computer system. Also featured is an operating system for execution with a multiprocessor computer system and a multiprocessor computer including such an operating system for execution therein.

Abstract: A time-weighted metric is associated with each line of data that is being held in a data cache. The value of the metric is recomputed as the lines are accessed and the metric value is used to group cache lines for paging purposes. The metrics are computed and stored and the stored metrics are maintained by linking the storage locations together in several linked lists that allow the metrics to be easily manipulated for updating purposes and for determining which metrics represent the most active cache lines. In particular, indices are maintained which identify linked lists of metrics with similar values. At regular predetermined time intervals, these indices are then used to assemble an ordered linked list of metrics corresponding to cache lines with similar metric values. This ordered list can be traversed in order to select cache lines for removal.

Abstract: A method for automatically finding the transition interval from a fast write to a delayed fast write, in a mass storage system in which the mass storage system has a plurality of disk drive storage elements controlled by a disk drive controller, the controller having a cache memory through which all data writes pass, and the controller receiving commands and data from at least one host computer.

Abstract: In a computer or microprocessor system having a plurality of resources making memory requests, a caching system includes a source tag generator which, depending on the embodiment, could reside in the requesting system resource, in a bus arbiter, or in a combination of a bus arbiter and a switch arbiter, or elsewhere. The system also includes cache control circuitry capable of using the source tag to make cacheability decisions. The cache control circuitry, and therefore the cacheability decisions, could be fixed—e.g., by a user—or could be alterable based on a suitable algorithm—similar, e.g., to a least-recently-used algorithm—that monitors cache usage and memory requests. The caching system is particularly useful where the cache being controlled is large enough to cache the results of I/O and similar requests and the requesting resources are I/O or similar resources outside the core logic chipset of the computer system.

Abstract: An apparatus comprising one or more memory blocks in a programmable logic device. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.