Abstract: A method for distinguishing carbon nanotubes comprising: providing a conductive substrate and applying an insulating layer on the conductive substrate; forming a carbon nanotube structure on a surface of the insulating layer, the carbon nanotube structure includes at least one carbon nanotube; placing the carbon nanotube structure under a scanning electron microscope, adjusting the scanning electron microscope with an accelerating voltage ranging from 5˜20 KV, a dwelling time ranging 6˜20 microseconds and a magnification ranging from 10000˜100000 times; taking photos of the carbon nanotube structure with the scanning electron microscope; and, obtaining a photo of the carbon nanotube structure, the photo shows the at least one carbon nanotube and a background.

Abstract: A fourth impurity region includes a first region facing a bottom portion of a trench and a part of a second impurity region and a second region facing the second impurity region. A first impurity region includes a third region in contact with a side surface of the trench, the second impurity region, the first region, and a second region and a fourth region which is located on a side of a second main surface relative to the third region, electrically connected to the third region, and lower in impurity concentration than the third region. A surface of the first region facing the second main surface is located on the side of the second main surface in a direction perpendicular to the second main surface relative to a surface of the second region facing the second main surface.

Abstract: A method of forming fully aligned vias in a semiconductor device includes forming an Mx level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level interconnect is recessed below the Mx interlevel dielectric or a dielectric is selectively deposited on the Mx interlevel dielectric. The method also includes laterally etching the exposed upper portion of the Mx interlevel dielectric bounding the recess or laterally etching the selectively deposited dielectric. A dielectric cap layer and an Mx+1 level interlevel dielectric is deposited on top of the Mx interlevel dielectric, and a via opening is formed.

Abstract: A semiconductor structure including an electrostatic discharge (ESD) diode with an increased junction area and a vertical field effect transistor (FET) formed on a same substrate is provided. The ESD diode is formed by forming a first doped semiconductor segment merging bottom portions of a pair of semiconductor fins and then forming a second doped semiconductor segment having a conductivity type opposite to that of each of the first doped semiconductor segment and the pair of semiconductor fins. A U-shaped p-n junction is present between the second doped semiconductor segment and the first doped semiconductor segment and the second doped semiconductor segment and the pair of semiconductor fins.

Abstract: A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first TiN layer to contact the first high-dielectric layer, and a first gate metal on the first TiN layer, the second gate stack includes a second high-dielectric layer, a second TiN layer to contact the second high-dielectric layer, and a second gate metal on the second TiN layer, the third gate stack includes a third high-dielectric layer, a third TiN layer to contact the third high-dielectric layer, and a third gate metal on the third TiN layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth TiN layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth TiN layer, the first through fourth thicknesses of the TiN layers being different.

Abstract: After forming a trench extending through a (100) silicon layer and a buried insulator layer and into a (111) silicon layer of a semiconductor-on-insulator (SOI) substrate, and prior to epitaxial growth of a Group III nitride material from a sub-surface of the (111) silicon layer that is exposed by the trench, a first sidewall spacer including a first dielectric material that can effectively prevent Group III elements from diffusing into silicon of the SOI substrate during the high temperature epitaxial growth of the Group III nitride materials is formed on sidewalls of the trench, following by forming a second sidewall spacer on the first sidewall spacer. The second sidewall spacer includes a second dielectric material that provides better growth selectivity towards the Group III nitride material than the first dielectric material, thus facilitating the growth of the Group III nitride material from the sub-surface of the (111) silicon layer.

Abstract: A terahertz modulator based on low-dimension electron plasma wave, a manufacturing method thereof, and a high speed modulation method are provided. The terahertz modulator includes a plasmon and a cavity. The present disclosure discloses the resonance absorption mechanism caused by collective oscillation of electrons (plasma wave, namely, the plasmon). In order to enhance the coupling strength between the terahertz wave and the plasmon, a GaN/AlGaN high electron mobility transistor structure having a grating gate is integrated in a terahertz Fabry-Pérot cavity, and a plasmon polariton is formed arising from strong coupling of the plasmon and a cavity mode.

Abstract: An embodiment provides a light-emitting element comprising: a substrate; a light-emitting structure, which is arranged on the substrate, and which comprises a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; a light-transmissive conductive layer arranged on the second conductive semiconductor layer; and first and second electrodes electrically connected to the first and second conductive semiconductor layers, respectively, wherein the light-transmissive conductive layer has corrugated portions formed on a first surface thereof, which is directed to the second conductive semiconductor layer, and the density of the corrugated portions in the peripheral area of the light-transmissive conductive layer is larger than the density of the corrugated portions in the central area of the light-transmissive conductive layer.

Abstract: A printed circuit board having an improved heat radiation performance, and a light-emitting device including the same are provided. The printed circuit board includes a first electrode layer, a first insulation layer disposed on one surface of the first electrode layer, and a second electrode layer disposed on the first insulation layer. The first insulation layer includes a cavity formed through a part thereof. At least a portion of the one surface of the first electrode layer may be exposed to the outside through the cavity.

Abstract: A display device, which includes a plurality of unit pixels, includes a plurality of first electrodes respectively corresponding to the plurality of unit pixels, an insulating layer which includes a plurality of through holes, a light emitting element layer, and a second electrode. Each of the plurality of through holes have inner surfaces including a forwardly tapered surface, which is inclined in a direction of enlarging the apertures toward a light emitting direction, and a reversely tapered surface, which is inclined in a direction of reducing the apertures toward the light emitting direction. The forwardly tapered surface is formed between the unit pixels arranged side by side in the first direction. The reversely tapered surface is formed between the unit pixels arranged side by side in the second direction.

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of first fin structures in a peripheral region of a substrate and a plurality of second fin structures in a core region of the substrate, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure and a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure together with each second dummy gate electrode layer, forming a first gate oxide layer on the exposed portion of each first fin structure, and then removing each second dummy gate oxide layer. The method further includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.

Abstract: Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“PoP”) with enhanced tolerance for warping. In one such packaged microelectronic device, at least one redistribution layer includes first interconnect pads on a lower surface and second interconnect pads on an upper surface of the at least one redistribution layer. Interconnect structures are on and extend away from corresponding upper surfaces of the second interconnect pads. A microelectronic device is coupled to an upper surface of the at least one redistribution layer. A dielectric layer surrounds at least portions of shafts of the interconnect structures. The interconnect structures have upper ends thereof protruding above an upper surface of the dielectric layer a distance to increase a warpage limit for a combination of at least the packaged microelectronic device and one other packaged microelectronic device directly coupled to protrusions of the interconnect structures.

Abstract: A semiconductor device includes a first semiconductor die, a second semiconductor die and a plurality of supporting structures. The first semiconductor die includes a plurality of first bumps disposed adjacent to a first active surface thereof. The second semiconductor die includes a plurality of second bumps disposed adjacent to a second active surface thereof. The second bumps are bonded to the first bumps. The supporting structures are disposed between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die. The supporting structures are electrically isolated and are disposed adjacent to a peripheral region of the second active surface of the second semiconductor die.

Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate.

Abstract: There is provided a semiconductor multilayer structure, including: an n-type GaN layer; and a p-type GaN layer which is formed on the n-type GaN layer and into which Mg is ion-implanted, and generating an electroluminescence emission having a peak at a photon energy of 3.0 eV or more, by applying a voltage to a pn-junction formed by the n-type GaN layer and the p-type GaN layer.

Abstract: An organic light-emitting diode (OLED) display device is provided having a color emission layer including a plurality of organic light-emitting elements in a first arrangement and an electronics layer. The electronics layer includes a plurality of pixel drive circuits each including an electrode contact. The electronics layer includes a plurality of independently addressable sub-regions each sub-region including an identical pattern of electrode contacts created using a single reticle exposure. Each sub-region is orientated differently within a plane such that the first arrangement of light-emitting elements is electrically connected to the patterned electronics layer.

Abstract: Semiconductor devices and FinFET devices are disclosed. A substrate has first and second regions. First and second gates are on the substrate in the first region, and a first end sidewall of the first gate is faced to a second end sidewall of the second gate. Third and fourth gates are on the substrate in the second region, and a third end sidewall of the third gate is faced to a fourth end sidewall of the fourth gate. A dielectric layer is between the first and second gates and between the third and fourth gates. The first and second regions have different pattern densities, and an included angle between the substrate and a sidewall of the dielectric layer between the first and second gates is different from an included angle between the substrate and a sidewall of the dielectric layer between the third and fourth gates.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge of the package substrate and an edge of the first region. A semiconductor die is disposed on the package substrate in the first region. A three-dimensional (3D) antenna is disposed on the package substrate in the second region. The 3D antenna includes a planar structure portion and a bridge or wall structure portion. A molding compound encapsulates the semiconductor die and at least a portion of the 3D antenna. A conductive shielding element is inside the molding compound or partially covers the molding compound. A semiconductor package assembly having the semiconductor package is also provided.

Abstract: A semiconductor device includes line patterns extending in a first direction, and separated from each other in a second direction perpendicular to the first direction. The plurality of line patterns includes at least two line sets, and each of the line sets includes four line patterns consecutively disposed in the second direction and having a length which varies based on location, and the at least two line sets have substantially an identical length.