Abstract: To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first bump on the first region and a second bump on the second region; forming a first doped layer on the first fin-shaped structure and the first bump; and forming a second doped layer on the second fin-shaped structure and the second bump.

Abstract: A first channel structure includes SixGe1-x and a second channel structure includes a group III-V compound material. First and second gate stacks are formed on the first and second channel structures. An insulating layer is formed on the gate stacks and the channel structures and is removed from the first channel structure to form a spacer on sidewalls of the first gate stack. First raised source and drain layers are formed on the first channel structure. The insulating layer is removed from the second channel structure to form a spacer on sidewalls of the second gate stack. The surfaces of the first and second channel structures and first source and drain layers are oxidized. The oxide layers are treated by a cleaning process that selectively removes the second native oxide layer only. Second raised source and drain layers are formed on the second channel structure. A CMOS structure is disclosed.

Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Abstract: A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.

Abstract: An organic electroluminescent display device includes a first substrate having a pixel area including a plurality of pixels each including a plurality of sub pixels, a light emitting devices are provided in correspondence with the sub pixels, and a partition layer covering a peripheral portion of each of the sub pixels; and a second substrate having a sensing unit including a first electrode pattern extending in one direction and a second electrode pattern extending in a direction intersecting the one direction, and the first electrode pattern and the second electrode pattern is provided out of contact from each other. The first electrode pattern is located to overlap the partition layer so as to enclose the sub pixels. The first electrode pattern included in the sensing unit encloses the sub pixels, and thus light is prevented from leaking to adjacent sub pixels.

Abstract: A display device includes a gate line and a data line on a first substrate. A first passivation layer disposed thereon has a first contact hole. A second passivation layer on the first passivation layer has a second contact hole. A common electrode is disposed on the second passivation layer and a residual pattern is disposed on a drain electrode. A third passivation layer, having a third contact hole, is disposed on the common electrode. A pixel electrode, connected to the drain electrode, is disposed on the third passivation layer. A groove is defined between the first and second passivation layers. The common electrode has a open circuit from the residual pattern thereof.

Abstract: Devices and method related to stacked duplexers. In some embodiments, an assembly may include a first wafer-level packaging (WLP) device having a radio-frequency (RF) shield. The assembly may also include a second WLP device having an RF shield, the second WLP device positioned over the first WLP device such that the RF shield of the second WLP device is electrically connected to the RF shield of the first WLP device.

Abstract: Semiconductor devices are provided. The semiconductor device includes a first fin portion and a second fin portion arranged on a substrate and extended in a first direction, the first fin portion and the second fin portion being spaced apart from each other in the first direction, a field insulating layer between the first fin portion and the second fin portion and having an upper surface thereof lower than an upper surface of the first fin portion, a first metal gate extended in a second direction on the first fin portion and a silicon gate extended in the second direction on the field insulating layer and contacting the field insulating layer.

Abstract: A method of fabricating a semiconductor device includes: providing a semiconductor substrate including a hard mask layer; performing, using the hard mask layer, etching to the semiconductor substrate to form a fin-type structure and a groove; forming an isolation material layer in the regions between adjacent fins of the fin-type structure and in the groove; removing a portion of the isolation material layer that is located above the hard mask layer to form a shallow trench isolation; and forming a second mask layer over the hard mask layer, the second mask layer having an opening above the shallow trench isolation; performing ion implantation to the shallow trench isolation through the opening; removing the second mask layer and the hard mask layer; and removing a portion of the isolation material layer located in the regions between adjacent fins of the fin-type structure and a portion of the shallow trench isolation.

Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.

Abstract: Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor.

Abstract: Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.

Abstract: A display device includes an element substrate including a display area where a plurality of self-light-emitting elements are formed, and a driver IC disposed outside the display area in the element substrate. A first metal layer is disposed on the reverse side of the element substrate at a position opposite to the display area. A second metal layer is disposed with a space between the first metal layer and the second metal layer on the reverse side of the element substrate at a position opposite to the driver IC.

Abstract: Some features pertain to an integrated device that includes a first integrated circuit (IC) package, a flexible connector and a second integrated circuit (IC) package. The first integrated circuit (IC) package includes a first die, a plurality of first interconnects, and a first dielectric layer encapsulating the first die. The flexible connector is coupled to the first integrated circuit (IC) package. The flexible connector includes the first dielectric layer, and an interconnect. The second integrated circuit (IC) package is coupled to the flexible connector. The second integrated circuit (IC) package includes the first dielectric layer, and a plurality of second interconnects. The first integrated circuit (IC) package, the second integrated circuit (IC) package, and the flexible connector are coupled together through at least a portion (e.g., contiguous portion) of the first dielectric layer. In some implementations, the flexible connector comprises a dummy metal layer.

Abstract: A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction.

Abstract: A semiconductor device (100) comprising a leadframe with a pad (101) and elongated leads (103) made of a base metal plated with a layer enabling metal-to-metal bonding; a semiconductor chip (110) attached to the pad, the chip having terminals. A metallic wire connection (130) from a terminal to a respective lead, the connection including a first ball bond by a first squashed ball (131) attached to the terminal, and a first stitch bond (132) attached to the lead. A second squashed ball (150) of the wire metal attached to the lead as a second ball bond adjacent to the first stitch bond (132). A package (170) of a polymeric compound encapsulating the chip, wire connection, second ball and at least a portion of the elongated lead, the compound adhering to the materials of the encapsulated entities.

Abstract: FinFET devices and methods of forming the same are disclosed. One FinFET device includes a substrate with first and second fins in a first region and third and fourth fins in a second region, and first to fourth gates respectively across the first to fourth fins. The first end sidewall of the first gate is faced to the second end sidewall of the second gate, and a first opening is formed between the first and second end sidewalls. The third end sidewall of the third gate is faced to the fourth end sidewall of the fourth gate, and a second opening is formed between the third and fourth end sidewalls. The first and second regions have different pattern densities, and the included angle between the sidewall of the first opening and the substrate is different from the included angle between the sidewall of the second opening and the substrate.

Abstract: A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.

Abstract: The present disclosure provides die cutting methods and semiconductor dies. A semiconductor substrate has a test region, isolation regions, and core regions. A device layer, an interconnection layer, and a soldering pad layer are formed on the semiconductor substrate. The soldering layer includes a plurality of soldering pads. A passivation layer covers the soldering pads and the interconnect layer, and is etched to form trenches on the soldering pads above the core regions and the test region. The passivation layer, the interconnect layer, and the device layer are etched to form isolation trenches at junctions of the isolation region and the test region, disconnecting the passivation layer, the interconnect layer and the device layer. A cutting process is performed along the test region, each of the semiconductor substrate, the device layer, the interconnect layer and the soldering pad layer is cut in two.