Abstract: A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F2. This array of threshold switching devices is suitable for a variety of memory or other applications including PRAM, MRAM, RRAM, FRAM, OPT-RAM and 3-D memory.

Abstract: An organic light-emitting device includes a first substrate, a light-emitting structure layer, a first electrode layer, a second electrode layer, a second substrate, first conduction members, a second conduction member and protection structures. The light-emitting structure layer is disposed on the first substrate. The first electrode layer is disposed on the light-emitting structure layer and includes pad-like patterns. The second electrode layer is disposed between the light-emitting structure layer and the first substrate. The second substrate is adhered on the first electrode layer and includes a first circuit and a second circuit. The first circuit includes a continuous pattern and contact portions. The first conduction members are connected between the first circuit and the first electrode layer. The second conduction member is connected between the second circuit and the second electrode layer.

Abstract: A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality of solder bumps, the plurality of protrusions includes sharp tips that penetrate the plurality of solder bumps, and a permanent electrical interconnection is established by physical contact between the plurality of protrusions and the plurality of solder bumps including a metallurgical joint.

Abstract: A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the OLED display includes an OLED formed over a substrate, the OLED including a first electrode, a second electrode formed over the first electrode and an intermediate layer interposed between the first and second electrodes. A pixel defining layer is formed over the substrate and adjacent to the OLED, and a protection layer is formed over the second electrode and configured to protect the OLED. A thin-film encapsulating layer is formed over the protection layer and sealing the OLED so as to protect the OLED from the environment, at least a part of the thin-film encapsulating layer contacting the pixel defining layer.

Abstract: Provided is an oxide semiconductor thin film transistor with low parasitic capacitance and high reliability. A thin film transistor includes a substrate, an oxide semiconductor layer including a channel region, a source region, and a drain region, a gate insulating film, and a gate electrode. The gate insulating film includes one layer or two layers, at least one of the layers of the gate insulating film is a patterned gate insulating film located at a position separated from the source electrode and the drain electrode. A length of a lower surface of the patterned gate insulating film in a channel length direction is greater than a length of a lower surface of the gate electrode in the channel length direction. The length of the lower surface of the patterned gate insulating film in the channel length direction is greater than a length of the channel region in the channel length direction. The source region and the drain region have a higher hydrogen concentration than the channel region.

Abstract: A display panel and a display device including the display panel are provided. The display panel includes data lines and scan lines arranged to be intersected, and a sensing antenna. The data lines and the scan lines are located in a display region of the display panel, and define multiple sub-pixels. The sensing antenna includes multiple sensing coils and is at least partly located in the display region of the display panel, and projections of the data lines and/or the scan lines cover projections of the sensing coils in a direction perpendicular to a surface of the display panel, in order to avoid affection on an aperture ratio of the display panel caused by the sensing coils located in the display region.

Abstract: An integrated circuit package with improved reliability and methods for creating the same are disclosed. More specifically, integrated circuit packages are created using one or more sacrificial layers that provide support for ink printed wires prior to package processing, but are removed during package processing. Once each of the sacrificial layers is removed, molding compound is placed around each ink printed wire, which may have a substantially rectangular cross section that can vary in dimension along a length of a given wire. While substantially surrounding each wire in and of itself improves reliability, removing non-conductive paste, fillets, or other adhesive materials also minimizes adhesion issues between the molding compound and those materials, which increases the bond of the molding compound to the package and its components. The net result is a more reliable integrated circuit package that is less susceptible to internal cracking and wire damage.

Abstract: The present invention discloses an array substrate, a display panel and a display device. The array substrate includes a substrate, a gate line and a data line arranged on the substrate, and a thin film transistor arranged in an overlapping region where the gate line and the data line are overlapped; wherein an orthogonal projection of the thin film transistor on the substrate covers an orthogonal projection of the overlapping region of the gate line and the data line on the substrate. Because of design of a location of the thin film transistor according to the present invention, the opening ratio can be increased, the slightly rubbing region adjacent to the thin film transistor can be reduced; and, because of the closed channel region, levels at various positions of the thin film transistor can be uniform, and a bigger contact area provided for the supporting post, thereby increasing supporting ability of the supporting post and compressive property of the panel.

Abstract: Provided herein are semiconductor devices with through electrodes and methods of fabricating the same. The methods may include providing a semiconductor substrate having top and bottom surfaces facing each other, forming on the top surface of the semiconductor substrate a main via having a hollow cylindrical structure and a metal line connected to the main via, forming an interlayered insulating layer on the top surface of the semiconductor substrate to cover the main via and the metal line, removing a portion of the semiconductor substrate to form a via hole exposing a portion of a bottom surface of the main via, and forming in the via hole a through electrode that is electrically connected to the main via. The bottom surface of the main via is overlapped by a circumference of the via hole, when viewed in a plan view.

Abstract: A light emitting element manufacturing method of allowing a semiconductor laminated part which includes a light emitting layer and includes a group-III nitride semiconductor to grow on a substrate surface in which protrusions are formed in a period which is larger than an optical wavelength of light emitted from the light emitting layer and is smaller than a coherent length of the light, includes: forming a buffer layer along the substrate surface having the protrusions; allowing crystal nuclei which have facet surfaces and are separated from each other to grow on the buffer layer such that the crystal nuclei include at least one protrusion; and allowing a planarization layer to grow on the buffer layer in which the crystal nuclei are formed.

Abstract: A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having low off-state current (current in an off state) is provided. Alternatively, a semiconductor device including the transistor is provided. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film over the oxide semiconductor film, and a conductive film overlapping with the oxide semiconductor film with the first insulating film or the second insulating film provided between the oxide semiconductor film and the conductive film. The composition of the oxide semiconductor film changes continuously between the first insulating film and the second insulating film.

Abstract: The semiconductor device comprises a semiconductor substrate (1), a photosensor (2) integrated in the substrate (1) at a main surface (10), an emitter (12) of radiation mounted above the main surface (10), and a cover (6), which is at least partially transmissive for the radiation, arranged above the main surface (10). The cover (6) comprises a cavity (7), and the emitter (12) is arranged in the cavity (7). A radiation barrier (9) can be provided on a lateral surface of the cavity (7) to inhibit cross-talk between the emitter (12) and the photosensor (2).

Abstract: A display device includes: a flexible substrate; a pixel over the flexible substrate, the pixel including a transistor and a display element; a first wiring for transmitting a signal to the pixel, the first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; an inorganic insulating layer on a higher level than the first wiring or the second wiring; and an organic insulating layer on a higher level than the inorganic insulating layer, wherein the inorganic insulating layer has an opening exposing a part of the upper surface of the first wiring or the second wiring is exposed, and the organic insulating layer is provided in such a way as to fill the opening.

Abstract: Disclosed is an organic light emitting diode display that includes a display panel having a display area that is defined with X and Y axes intersecting each other; and a plurality of pixels in the display panel, each comprising a first sub-pixel, a second sub-pixel and a third sub-pixel, wherein a shape of each of the first, second and third sub-pixels is defined by sides that are at a non-zero angle to the Y-axis or parallel to the X-axis, the first and second sub-pixels are substantially symmetrical to each other with respect to the X-axis, and the third sub-pixel is larger in size than the first and second sub-pixels.

Abstract: In accordance with an embodiment, semiconductor component having a compound semiconductor material based semiconductor device connected to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.

Abstract: A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.

Abstract: In some examples, a circuit package further includes an insulating layer and a first transistor extending through the insulating layer, where the first transistor includes a first control terminal on a top side of the insulating layer, a first source terminal on the top side of the insulating layer, and a first drain terminal on a bottom side of the insulating layer. The circuit package includes a second transistor extending through the insulating layer, where the second transistor includes a second control terminal on the top side of the insulating layer, a second source terminal on the bottom side of the insulating layer, and a second drain terminal on the top side of the insulating layer.

Abstract: The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method of manufacturing the same. The present invention provides a thin-film transistor provided with a source electrode (108), a drain electrode (109), a semiconductor layer (105), a gate electrode (103), and an insulating layer (104); wherein the semiconductor layer (105) contains a composite metal oxide obtained by adding to a first metal oxide an oxide having an oxygen dissociation energy that is at least 200 kJ/mol greater than the oxygen dissociation energy of the first metal oxide, whereby the amount of oxygen vacancy is controlled; and the insulating layer (104) is provided with an SiO2 layer, a high-permittivity first layer, and a high-permittivity second layer, whereby the dipoles generated at the boundary between the SiO2 layer and the high-permittivity layers are used to control the threshold voltage.

Abstract: An organic light emitting display device includes a plurality of pixel regions on a substrate, each having a sub-pixel region, a transmissive region and a peripheral region, a plurality of sub-pixel circuits in the sub-pixel region that control the sub-pixel region, a planarization layer that covers the sub-pixel circuits, a first electrode disposed on the planarization layer in the sub-pixel region, a second electrode disposed on the first electrode, and a plurality of wirings disposed at different levels over the substrate in the peripheral region. The wirings are arranged in at least double level configuration and include first wirings that extend in a first direction over the substrate, and second wirings that extend over the substrate in a second direction substantially perpendicular to the first direction.