Abstract: A transistor with a multi-layer active layer having at least one partial recess is provided. The transistor includes a channel layer arranged over a substrate. The channel layer has a first bandgap. The transistor includes a first active layer arranged over the channel layer. The first active layer has a second bandgap different from the first band gap such that the first active layer and the channel layer meet at a heterojunction. The transistor includes a second active layer arranged over the first active layer. The transistor also includes a dielectric layer arranged over the second active layer. The transistor further includes gate electrode having gate edges that are laterally adjacent to the dielectric layer. At least one gate edge of the gate edges is laterally separated from the second active layer by a first recess.

Abstract: The organic electroluminescence display device of an embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, and a sealing film that covers the plurality of pixels. The sealing film includes a first barrier layer, a base layer covering the top surface of the first barrier layer, an inter layer locally formed on the top surface of the base layer, and a second barrier layer covering the top surface of the base layer and the top surface of the inter layer. The inter layer is formed so as to cover a step on the top surface of the base layer.

Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

Abstract: A display panel including: a substrate; and a plurality of line banks arranged along a specific direction on the substrate, wherein the line banks are each formed of plural line segments connected to one another end to end, and each have a periodic structure.

Abstract: A two-dimensional heterostructure is synthesized by producing a patterned first two-dimensional material on a growth substrate. The first two-dimensional material is patterned to define at least one void through which an exposed region of the growth substrate is exposed. Seed molecules are selectively deposited either on the exposed region of the growth substrate or on the patterned first two-dimensional material. A second two-dimensional material that is distinct from the first two-dimensional material is then grown from the deposited seed molecules.

Abstract: The organic electroluminescence display device of an embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, and a sealing film that covers the plurality of pixels. The sealing film includes a first barrier layer, a base layer covering the top surface of the first barrier layer, an inter layer locally formed on the top surface of the base layer, and a second barrier layer covering the top surface of the base layer and the top surface of the inter layer. The inter layer is formed so as to cover a step on the top surface of the base layer.

Abstract: Provided are liquid crystal display and the method for manufacturing the same. According to an aspect of the present disclosure, there is provided a liquid crystal display device, including: a first substrate; a gate electrode disposed on the first substrate; a semiconductor pattern layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the semiconductor pattern layer and facing each other, wherein the gate electrode includes a reference plane and a protrusion protruding from the reference plane in a horizontal direction, and the protrusion overlaps the source electrode and the drain electrode.

Abstract: An organic electroluminescence (EL) device whose organic EL layer is less likely exposed to moisture. The organic EL device includes an organic EL layer; and a hygroscopic layer disposed with respect to at least one main surface of the organic EL layer. The hygroscopic layer includes: a hygroscopic film containing a base material and a hygroscopic agent mixed in the base material; and a pair of covering films each covering a different one of surfaces of the hygroscopic film in a thickness direction of the hygroscopic film. A region of the hygroscopic film that is in contact with one covering film whose distance from the organic EL layer is smaller than a distance of the other covering film from the organic EL layer contains the hygroscopic agent at a content rate lower than an average content rate of the hygroscopic agent in the hygroscopic film.

Abstract: A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.

Abstract: A light emitting element with a hexagonal planar shape, has: an n-side semiconductor layer; a p-side semiconductor layer provided on the n-side semiconductor layer; a plurality of holes that are provided to an area excluding three corners at mutually diagonal positions of the p-side semiconductor layer in plan view, and expose the n-side semiconductor layer; a first p-electrode provided in contact with the p-side semiconductor layer; second p-electrodes provided to three corners on the first p-electrode; and an n-electrode that is provided on the first p-electrode and is electrically connected to the n-side semiconductor layer through the plurality of holes.

Abstract: A repairable matrix-addressed system includes a system substrate, an array of electrically conductive row lines, and an array of electrically conductive column lines disposed over the system substrate. The row lines extend over the system substrate in a row direction and the column lines extend over the system substrate in a column direction different from the row direction to define an array of non-electrically conductive intersections between the row lines and the column lines. An array of electrically conductive line segments is disposed over the system substrate. The line segments extend over the system substrate substantially parallel to the row direction and have a line segment length that is less than the distance between adjacent column lines. Each line segment is electrically connected to a column line. One or more devices are electrically connected to each row line and to each line segment adjacent to the row line.

Abstract: In one embodiment, a flexible device is provided. The flexible device may include a flexible substrate, a buffer layer, a light reflective layer, and a device layer. The buffer layer is located on the flexible substrate. The light reflective layer is located on the flexible substrate, wherein the light reflective layer has a reflection wavelength of 200 nm˜1100 nm, a reflection ratio of greater than 80%, and a stress direction of the light reflective layer is the same as a stress direction of the flexible substrate. The device layer is located on the light reflective layer and the buffer layer.

Abstract: An electronic static discharge protection apparatus provided. A plurality of ESD circuits serially coupled between a pad and a internal circuit, a first stage ESD circuit includes a ESD element directly coupled to the pad, and a last stage ESD circuit includes an inductive element directly coupled to the internal circuit, so as to improve electronic discharge protecting ability of the ESD protection apparatus and increase circuit operation bandwidth without signal loss attenuation.

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Abstract: A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.

Abstract: A via opening is provided in an interconnect dielectric material. Prior to line opening formation, a continuous layer of a sacrificial material is formed lining the entirety of the via opening. An organic planarization layer (OPL) and a photoresist that contains a line pattern are formed above the interconnect dielectric material. The line pattern is then transferred into an upper portion of the interconnect dielectric material, while maintaining a portion of the OPL and a portion of the continuous layer of sacrificial material within a lower portion of the via opening. The remaining portions of the OPL and the sacrificial material are then removed from the bottom portion of the via opening. A combined via opening/line opening is provided in which the via opening has a well controlled profile/geometry. An interconnect metal or metal alloy can then be formed into the combined via opening/line opening.

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract: An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract: To provide a display device with excellent display quality, in a display device including a signal line, a scan line, a transistor, a pixel electrode, and a common electrode in a pixel, the common electrode is included in which an extending direction of a region overlapping with the signal line differs from an extending direction of a region overlapping with the pixel electrode in a planar shape and the extending directions intersect with each other between the signal line and the pixel electrode. Thus, a change in transmittance of the pixel can be suppressed; accordingly, flickers can be reduced.