Abstract: Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier. A semi-insulating layer is epitaxially formed on the bottom barrier, laterally adjacent to the channel. The semi-insulating layer is formed in such a way that stress is induced onto the channel. A CMOS transistor is formed on the channel.

Abstract: A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film.

Abstract: An apparatus includes a package, a wall and a lid. The package may be configured to mount two chips configured to generate one or more signals in a millimeter-wave frequency range. The wall may be formed between the two chips. The wall generally has a plurality of conductive arches that attenuate an electromagnetic coupling between the two chips in the millimeter-wave frequency range. The lid may be configured to enclose the chips to form a cavity.

Abstract: The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method of manufacturing the same. The present invention provides a thin-film transistor provided with a source electrode (108), a drain electrode (109), a semiconductor layer (105), a gate electrode (103), and an insulating layer (104); wherein the semiconductor layer (105) contains a composite metal oxide obtained by adding to a first metal oxide an oxide having an oxygen dissociation energy that is at least 200 kJ/mol greater than the oxygen dissociation energy of the first metal oxide, whereby the amount of oxygen vacancy is controlled; and the insulating layer (104) is provided with an SiO2 layer, a high-permittivity first layer, and a high-permittivity second layer, whereby the dipoles generated at the boundary between the SiO2 layer and the high-permittivity layers are used to control the threshold voltage.

Abstract: Provided is a bonding wire for a semiconductor package and a semiconductor package including the same. The bonding wire for the semiconductor package may include a core portion including silver (Ag), and a shell layer surrounding the core portion, having a thickness of 2 nm to 23 nm, and including gold (Au). The semiconductor package may include a package body having a first electrode structure and a second electrode structure, a semiconductor light emitting device comprising a first electrode portion and a second electrode portion electrically connected to the first electrode structure and the second electrode structure, and a bonding wire connecting at least one of the first electrode structure and the second electrode structure to the semiconductor light emitting device.

Abstract: An array substrate and a method of manufacturing the same, a display panel and a display device are disclosed. The array substrate includes: a base substrate, and a first conductive layer, a first insulation layer, a semiconductor layer, a second conductive layer, a second insulation layer, and a third conductive layer that are sequentially formed on the base substrate. The first conductive layer includes a gate electrode pattern, the semiconductor layer includes an active area pattern, and the second conductive layer includes a source-drain electrode pattern; the second insulation layer is provided with a connection via hole between the third conductive layer and the second conductive layer; and the semiconductor layer further includes a spacing pad pattern in a region where the connection via hole is provided.

Abstract: A one-time programmable non-volatile memory device includes a first conductivity type well region located in a semiconductor substrate, a selection gate electrode and a floating gate electrode located on the substrate, a first doped region located between the selection gate electrode and the floating gate electrode, a second conductivity type source region located on one side of the selection gate electrode, and a second conductivity type drain region located on one side of the floating gate electrode, wherein a depth of the drain region has a depth shallower than that of the first doped region with respect to a top surface of the substrate.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.

Abstract: A semiconductor device includes a first nitride semiconductor layer, a source electrode on the first nitride semiconductor layer, a drain electrode on the first nitride semiconductor layer, a gate electrode on the first nitride semiconductor layer and between the source electrode and the drain electrode, a gate field plate electrode that is separated from the first nitride semiconductor layer, and includes one end in direct contact with the gate electrode, and the other end positioned between the gate electrode and the drain electrode, a first interlayer insulating film that is separated from the gate electrode and is between the gate field plate electrode and the first nitride semiconductor layer, and a second interlayer insulating film that is between the gate electrode and the first interlayer insulating film and has a dielectric constant higher than a dielectric constant of the first interlayer insulating film.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The semiconductor device also includes a first dielectric layer over the semiconductor substrate and surrounding the first conductive feature. The semiconductor device further includes a second conductive feature over the first conductive feature, and the second conductive feature extends into the first conductive feature. In addition, the semiconductor device includes a second dielectric layer over the first dielectric layer and surrounding the second conductive feature. The semiconductor device also includes an etch stop layer between the first dielectric layer and the second dielectric layer. The etch stop layer surrounds the first conductive feature, and a bottom surface of the second conductive feature is above the etch stop layer.

Abstract: A semiconductor device including a substrate, insulators, a gate dielectric layer, a first gate structure and a second gate structure is provided. The substrate includes trenches, a first semiconductor fin and a second semiconductor fin. The first gate structure is disposed on the gate dielectric layer and partially covers the first semiconductor fin. The first gate structure includes a first metal gate and a first dielectric cap covering the first metal gate. The second gate structure is disposed on the gate dielectric layer and partially covers the second semiconductor fin. The second gate structure includes a second metal gate and a second dielectric cap covering the second metal gate. Work function of the first metal gate is smaller than work function of the second metal gate and thickness of the first dielectric cap is smaller than thickness of the second dielectric cap.

Abstract: According to an embodiment, a semiconductor memory device comprises a first region, a second region, and a third region. The first region includes: a part of a stacked body that includes a plurality of conductive layers; and a memory columnar body which has its side surface covered by the stacked body and configures a memory string. The second region includes: a contact; a contact portion connected to the contact, of the conductive layer; and a plurality of first columnar bodies. The third region includes a second columnar body. In a plane parallel to the substrate, a total area of the second columnar body in a small region that has the same area as one or more contact portions, in the third region is larger than a total area of the first columnar body in the one or more contact portions.

Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.

Abstract: There is provided an apparatus includes a substrate having a main surface, a wordline buried in the substrate and a bitline buried in a shallower area than the wordline in the substrate.

Abstract: A display panel, a preparing method thereof and a display device are provided. The method of preparing a display panel includes steps of: coating an alignment material on both a display region of an array substrate and an electrode region of the array substrate located around a periphery of the display region; aligning the alignment material; assembling the aligned array substrate and an aligned color filter substrate into an assembly; cutting the assembly of the array substrate and the color filter substrate into a plurality of display panel units, such that the electrode region of the array substrate is not covered by the color filter substrate in each of the display panel units; and removing the alignment material covering the electrode region of the array substrate so as to expose the electrode region.

Abstract: There is provided a solid-state imaging device including: one or more photoelectric conversion elements provided on side of a first surface of a semiconductor substrate; a through electrode coupled to the one or more photoelectric conversion elements, and provided between the first surface and a second surface of the semiconductor substrate; and an amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate, in which the one or more photoelectric conversion elements are coupled to a gate of the amplifier transistor and the floating diffusion via the through electrode.

Abstract: A hollow frame is configured to surround the periphery of a substantially self-supporting flip-chip light emitting device. The frame may be shaped to also contain a wavelength conversion element above the light emitting surface of the light emitting device. The lower surface of the light emitting device, which is exposed through the hollow frame, includes contact pads coupled to the light emitting element for surface mounting the light emitting module on a printed circuit board or other fixture. The flip-chip light emitting device may include a patterned sapphire substrate (PSS) upon which the light emitting element is grown, the patterned surface providing enhanced light extraction from the light emitting element, through the patterned sapphire substrate.

Abstract: A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.

Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.

Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first ridge portion embedded in the first concave and the drain includes a second ridge portion embedded in the second concave, wherein the first and second ridge portions extend along a height direction of the semiconductor fin.