Abstract: An electronic package is provided. The electronic package includes an insulator having a recessed portion formed therein; an electronic element embedded in the recessed portion and having a sensing region exposed from the insulator; and a conductive structure disposed on the insulator and electrically connected with the electronic element. The overall thickness of the electronic package is reduced by embedding the electronic element which is embedded in the recessed portion.

Abstract: The present invention provides a lateral IGBT transistor comprising a bipolar transistor and an IGFET. The lateral IGBT comprises a low resistive connection between the drain of the IGFET and the base of the bipolar transistor, and an isolating layer arranged between the IGFET and the bipolar transistor. The novel structure provides a device which is immune to latch and gives high gain and reliability. The structure can be realized with standard CMOS technology available at foundries.

Abstract: A wide trench having a width W1 and narrow trenches having a width W2 that is less than W1 are formed in a dielectric layer, the wide trench extending deeper in outer regions than in a central region. A trench modification step changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench.

Abstract: A semiconductor device includes a SiC layer that has a first surface and a second surface, a first electrode in contact with the first surface, a first SiC region of a first conductivity type in the SiC layer, a second SiC region of a second conductivity type in the SiC layer and surrounding a portion of the first SiC region, a third SiC region of the second conductivity type in the SiC layer and surrounding the second SiC region, the third SiC region having an impurity concentration of the second conductivity type lower than that of the second SiC region, and a fourth SiC region of the second conductivity type in the SiC layer between the second SiC region and the third Sic region, the fourth SiC region having an impurity concentration of the second conductivity type higher than that of the second SiC region.

Abstract: An organic light emitting diode display includes a plurality of switches, a plurality of organic light emitting diodes respectively connected to the switches, and a polarization layer on the organic light emitting diodes. The polarization layer includes a light blocking area and a plurality of color filters. The light blocking area has a plurality of openings respectively exposing the organic light emitting diodes. The color filters respectively fill the openings. A first dot opening includes a first red opening, a first green opening, and a first blue opening elongated in a first direction. A second dot opening includes a second red opening, a second green opening, and a second blue opening elongated in a second direction crossing the first direction.

Abstract: A method is provided that includes forming a first vertical bit line disposed in a first direction above a substrate, forming a first word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, forming a first memory cell comprising a nonvolatile memory material at an intersection of the first vertical bit line and the first word line, forming a transistor above the substrate, and forming a first bit line select device coupled between the first vertical bit line and the transistor.

Abstract: A thin film transistor (TFT) substrate which may facilitate subsequent TFT processing by reducing an elevation difference on the top surface of the substrate is disclosed. Aspects include an organic light-emitting apparatus including the TFT substrate, a method of manufacturing the TFT substrate, and a method of manufacturing the organic light-emitting apparatus. In one aspect the TFT substrate includes: a substrate; a height adjusting layer that is disposed on the substrate and has a thickness in a first region greater than a thickness in a second region; and a TFT that is formed on the height adjusting layer to correspond to the second region of the height adjusting layer.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

Abstract: A method of forming a semiconductor device comprises forming a first fin on a substrate, depositing an insulator layer on the substrate adjacent to the first fin, removing a first portion of the insulator layer to expose a first portion of a sidewall of the first fin, depositing a layer of spacer material over the first portion of the sidewall of the first fin, removing a second portion of the insulator layer to expose a second portion of the sidewall of the first fin, depositing a first glass layer including a first doping agent over the exposed second portion of the sidewall of the first fin, and performing a first annealing process to drive the first doping agent into the first fin.

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface, a first electrode on the first surface, a second electrode on the second surface, a first semiconductor region of a first conductivity type in the semiconductor layer, a second semiconductor region of a second conductivity type in an element region of the semiconductor layer between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the second semiconductor region and the first electrode, and a fourth semiconductor region of the second conductivity type in a termination region of the semiconductor layer inwardly of the first surface. A distance between the fourth semiconductor region and the second surface is greater than a distance between the second semiconductor region and the second surface.

Abstract: A semiconductor structure includes a first device, a second device, a first hole, a second hole, and a sealing object. The second device is contacted to the first device, wherein a chamber is formed between the first device and the second device. The first hole is disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference. The second hole is disposed in the second device and aligned to the first hole. The sealing object seals the second hole. The first end links with the chamber, and the first circumference is different from the second circumference.

Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.

Abstract: Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less.

Abstract: A light emitting device may include a substrate, a light emitting structure disposed under the substrate, the light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a first electrode configured to penetrate the second conductive semiconductor layer and the active layer, so as to come into contact with the first conductive semiconductor layer, a contact layer configured to come into contact with the second conductive semiconductor layer, a first insulation layer disposed between the second conductive semiconductor layer and the first electrode and between the active layer and the first electrode, the first insulation layer being provided for capping of a side portion and an upper portion of the contact layer, and a second electrode configured to penetrate the first insulation layer, so as to come into contact with the contact layer.

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract: An integrated capacitor can be fabricated with both electrodes formed by trenches for low resistance. According to one embodiment, the capacitor can comprise a first trench electrode, one or more dielectric layers, and a second trench electrode. The first trench electrode and the second trench electrode can be fabricated in different trenches to improve capacitance density and resistance of the integrated capacitor.

Abstract: A semiconductor device includes: a buffer layer formed over a substrate; a first semiconductor layer formed over the buffer layer by using a compound semiconductor; a second semiconductor layer formed over the first semiconductor layer by using a compound semiconductor; and a gate electrode, a source electrode, and a drain electrode formed over the second semiconductor layer, wherein the first semiconductor layer contains an impurity element serving as an acceptor and an impurity element serving as a donor; and in the first semiconductor layer, an acceptor concentration of the impurity element serving as the acceptor is greater than a donor concentration of the impurity element serving as the donor; and the donor concentration is greater-than over equal to 5×1016 cm?3.

Abstract: A semiconductor memory device according to an embodiment comprises a stacked body, a semiconductor layer, a charge accumulation layer, and a slit portion. The stacked body includes a plurality of control gate electrodes stacked above a substrate. The semiconductor layer has one end thereof connected to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. The slit portion extends in a direction of the substrate from a surface of the stacked body, wherein the slit portion has its longitudinal direction in a direction intersecting the first direction.

Abstract: Disclosed is a light emitting device. The light emitting device includes a body, first and second metal layers on a top surface of the body, a heat radiation plate disposed between the first and second metal layers and having a circular outline, a plurality of light emitting parts on the heat radiation plate, first and second bonding regions disposed on the first and second metal layers and electrically connected with the light emitting parts, and a molding member disposed on the heat radiation plate to cover the light emitting parts. Each of the light emitting parts includes a plurality of light emitting chips connected with each other, and a plurality of wires to electrically connect the light emitting chips with the first and second bonding regions, and the wires of each light emitting part are arranged a radial direction about a central of the heat radiation plate.

Abstract: One semiconductor device includes one parallel transistor for connecting in parallel multiple vertical transistors disposed in an active region on a semiconductor substrate. The parallel transistor includes semiconductor pillars that project out in a direction perpendicular to a main surface of the semiconductor substrate; a lower diffusion layer that is disposed below the semiconductor pillars; upper diffusion layers that are each disposed on an upper section of the semiconductor pillars; and gate electrodes disposed, with a gate insulator film therebetween, on the entire side surfaces of the semiconductor pillars. The upper diffusion layers are connected to one upper contact plug that is disposed over the upper diffusion layers.