Abstract: A surface mounted LED package includes a pair of metal contact plates, an LED mounted to one (or both) metal contact plates, and glue encapsulating the LED and holding the LED and both metal contact plates together to form a LED package to be soldered to a motherboard. The contact plates have side notches and bottom recesses of various shapes and dimensions, as well as through holes extending through the entire width of the contact plates to facilitate the glue flow for filling out the side notches and bottom recesses for improved solidifying of the LED package. The contact plates have portions uncovered by the glue to provide extended areas for soldering to a motherboard.

Abstract: A substrate assembly is disclosed including a substrate and a plurality of spring-biased electrical contacts formed thereon for establishing electrical contact with the lead elements of an IC device. The substrate assembly also comprises a layer of resilient conductive material formed on a surface of the substrate, the spring-biased electrical contacts being formed in the resilient conductive material layer in situ on the substrate. Each spring-biased electrical contact includes a surface or surfaces configured to bias against and electrically contact an IC device lead element. The present invention also encompasses methods of fabricating substrate assemblies according to the invention, including heat treating the substrate assembly after formation to achieve desired spring characteristics.

Abstract: A flip chip integrated package is described as including a chip encapsulated with a mold compound and mounted on a substrate. In one embodiment, the mold compound surrounds the chip, filling in space between the chip and the substrate. The substrate includes a plurality of openings through which the mold compound extrudes, forming molded buttons. In another embodiment, the substrate includes more numerous openings of a smaller diameter, which allow the mold compound to extrude through and create a molded rib. The molded buttons and the molded rib serve as a mount support feature. The substrate includes vents to allow trapped gas to be expelled from the package.

Abstract: A MOS semiconductor device includes n?-type surface regions, which are extended portions of an n?-type drift layer 12 extended to the surface of the semiconductor chip. Each n?-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n?-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 ?m or less.

Abstract: Flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an image sensor chip is bonded to the conductive traces. Discrete conductive elements are attached to the conductive traces and extend below a back surface of the image sensor chip. In a second embodiment, a secondary substrate having conductive traces formed thereon is secured to the transparent substrate. In a third embodiment, a backing cap having a full array of attachment pads is attached to the transparent substrate of the first embodiment or the secondary substrate of the second embodiment. In a fourth embodiment, the secondary substrate is a flex circuit having a mounting portion secured to the second surface of the transparent substrate and a backing portion bent over adjacent to the back surface of the image sensor chip.

Abstract: A routing element for use with a multichip module includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths that those provided by a multichip module substrate. The conductive traces may be carried upon a single surface of the routing element substrate, be carried internally by the routing element substrate, or include externally and internally carried portions. The routing element also includes a contact pad positioned at each end of each conductive trace thereof to facilitate electrical connection of each conductive trace to a corresponding terminal of the substrate or to a corresponding bond pad of a semiconductor device of the multichip module. Multichip modules are also disclosed, as are methods for designing the routing element and methods in which the routing element is used.

Abstract: A light emitting device is provided which has a structure for preventing degradation of a light emitting element due to water and oxygen contained in an interlayer insulating film formed between a TFT and the light emitting element. A TFT is formed on a substrate, an inorganic insulating film is formed on the TFT from an inorganic material and serves as a first insulating film, an organic insulating film is formed on the first insulating film from an organic material and serves as a second insulating film, and an inorganic insulating film is formed on the second insulating film from an inorganic material and serves as a third insulating film. Thus obtained is a structure for preventing the second insulating film from releasing moisture and oxygen. In order to avoid defect in forming the film, a portion of the third insulating film where a contact hole is formed is removed alone.

Abstract: A semiconductor device comprises a substrate having contact pads each covered by under bump metallurgy and a plurality of bump electrodes respectively provided on the under bump metallurgy covering the contact pads. According to one embodiment of the present invention, the semiconductor device is characterized by having at least one contact pad (e.g., a test contact pad) which is not provided with any bump electrode but still has under bump metallurgy provided thereon. According to another embodiment of the present invention, the semiconductor device is characterized by having at least a conductive line formed of the same material as the under bump metallurgy for interconnecting at least two of the contact pads. The present invention further provides methods of manufacturing the semiconductor devices.

Abstract: The present invention provides a semiconductor device whose reliability is improved by improving the adhesion strength of a metal plate or connecting chip, said plurality of electrodes and a lead frame with a molding resin. Further, the semiconductor device of the present invention prevents flow out of a conductive joining material to be employed for joining a lead terminal and the metal plate other than the joining range of the metal plate and the lead terminal, and mounts the metal plate at high precision. In a semiconductor device (a plastic package) in which a source electrode of a semiconductor chip and source terminal of a lead frame are electrically connected by a copper plate and sealed by a resin, the surface of the copper plate is roughened to improve the adhesion strength to a molding resin. Further, a stepped part is formed in the source terminal to prevent a conductive paste from flowing out. The structure is so formed as to fit claw parts in the lead frame.

Abstract: A flip chip semiconductor device has a cell forming layer assigned to macro-cells and input and output cells and a pad forming layer assigned to power supply pads for the macro-cells and input and output cells and signal pads for the input and output cells, and the signal pads are arranged outside of the power supply pads, whereby a package substrate to be assembled with the flip chip semiconductor device is simplified by virtue of the signal lines on a level with the signal pads, because any power supply pad is not an obstacle against the signal lines.

Abstract: An optical transistor is disclosed that provides a fast switching time, an amplified gain, and isolation. The optical transistor receives a small optical input signal at an optical base port, generates an amplified replica at an optical emitter port, and generates an inverted replica on a vertical light at an collector port. One embodiment of the optical transistor is implemented with a vertical lasing semiconductor optical amplifiers (VLSOA), wherein the ballast light is used a signal for the collector port.

Abstract: There is disclosed a flip chip semiconductor integrated circuit, which comprises an internal cell, an I/O buffer as an interface between the internal cell and an external unit, a solder ball, a GND or power supply wire, and an I/O buffer unit arranged on a chip. In this case, the components except the I/O buffer unit are formed in a unit and arranged on the chip, and the I/O buffer unit includes a signal solder ball for transferring signals with the external unit, an I/O buffer having a signal terminal connected to the signal solder ball, a first I/O buffer GND wire connected to a GND terminal of the I/O buffer, and a first I/O buffer power supply wire connected to a power supply terminal of the I/O buffer.

Abstract: Methods of correcting for overlay error, wherein the methods account for relative offset across the field of exposures of more than one photolithography projection system, as well as systems to perform the methods and apparatus produced therefrom. The methods include defining at least two zones within a field of a mask having substantially similar overlay error values. The methods further include modifying the coordinates of a feature of the mask in response to a correction for the zone to which the feature is mapped, where the correction corresponds to a nominal overlay error value for that zone.

Abstract: A semiconductor device that has a semiconductor die having at least two opposing major electrodes and a control electrode. Conductive clips, each having a base portion and a contact portion, are connected to respective electrodes at their bases by a respective layer of conductive material. A passivation layer is disposed on at least one of the electrodes and surrounds the layers of conductive material. The base portion and the contact portion of one of the clips are connected by an extension, which extends between the major surfaces of the semiconductor die.

Abstract: A light emitting diode has a substrate having a heat radiation conductive member therein, and a light emitting element mounted on the substrate. At least a part of the light emitting element is directly brought into contact and electrically connected with the heat radiation conductive member.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include depositing a fill layer upon a metal layer and subsequently polishing the fill layer. In some cases, the method may form a surface in which an upper surface of the fill layer is substantially level with at least one of the peaks associated with the surface roughness of the metal layer. In some cases, the surface may include portions of the metal layer and portions of the fill layer residing above the metal layer. In other cases, the method may include forming a surface in which the fill layer is arranged above the metal layer-fill layer interface. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained.

Abstract: A window-type ball grid array (WBGA) semiconductor package is proposed. A substrate is formed with an opening and a tape attach area around the opening. A polyimide tape having an aperture is applied over the tape attach area, allowing the aperture to be aligned with the opening of the substrate. A chip is mounted over the polyimide tape and electrically connected to the substrate via the opening by bonding wires, wherein the polyimide tape is interposed between the chip and the substrate so as not to leave any gaps between the chip and the substrate. A first encapsulant is formed to fill the opening and encapsulate the bonding wires. A second encapsulant is fabricated to encapsulate the chip. With no gaps between the chip and the substrate, the chip is firmly supported on the substrate during a molding process for fabricating the second encapsulant, thereby preventing chip cracks from occurrence.

Abstract: A QFP exposed pad package which includes leads exposed within the bottom surface of the package body of the package in addition to those gull-wing leads protruding from the sides of the package body. Those leads exposed within the bottom surface of the package body are created through the utilization of a standard leadframe with additional lead features that are electrically isolated subsequent to a molding process through the use of a partial saw method.

Abstract: A microcooling device is provided. The microcooling device includes a substrate, a microchannel array, and a condenser. A predetermined region of a lower surface of the substrate contacts a heat source. The microchannel array is placed on the substrate so that a coolant concentrating portion is opposite to the predetermined region of the lower surface. The condenser fixes the microchannel array, condenses vapor generated in a process of cooling the heat source, and allows the condensed vapor to flow into the microchannel array.

Abstract: A semiconductor device including a package body, a substrate contained within the package body and having a first side and an opposite second side, a first chip mounted on the first side of the substrate and within the package body, a second chip mounted on the second side of the substrate and within the package body and a plurality of leads each including an inner lead portion contained within the package body and an outer lead portion located outside the package body wherein each inner lead portion includes first and second bends to define a step configuration and wherein a distal end of each inner lead portion is mounted to the second side of the substrate.